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CS 481: Operating System Principles
Spring ’
Problem Set #2: Memory Management
Due: Thursday, March 5
Consider a system with the following features:
- 1 TB^1 of physical memory
- 8 KB frames
- the system is intended for high job throughput, and the majority of the jobs require less than 64 KB of memory – yes, that’s really small.
- Process size is constrained by the size of physical memory (no virtual memory)
1 What is the address size needed for this system? (5 pts)
1 TB = 240 bytes. Need 40-bit addresses for this system.
2 Would you choose a contiguous memory allocation scheme or paging? Why? (5 pts)
Since the processes are small, the simplicity (only need base and limit register) and low effective memory access latency of contiguous memory allocation makes it a good choice. In contrast, paging increases effective memory access latency, and therefore, decreases job throughput and turn-around time. In addition, paging doesn’t buy much since allocating contiguous frames for the small processes in general will not pose a big problem.
3 Considering a non-hierarchical paging scheme, draw a diagram to show which and how many bits of the virtual address are used for the page number and the page offset. (5 pts)
27-bit page number 13-bit offset
(^0) Showing your work may allow you to get partial credit. (^11) KB = 1, 024 bytes, 1MB = 1, 024KB, 1GB = 1, 024MB, 1TB = 1, 024GB
4 With 4 bytes per entry, how much memory is required for each process’ page table? ( pts)
physical memory: 1 TB = 240 bytes frame (page) size: 8 KB = 213 bytes
of frames (page table entries): 240 / 213 = 227 pages
page table size: 227 × 4 = 229 bytes = 512 MB
5 Suggest a hierarchical paging scheme that allows each page table to fit within a single page using a picture of the virtual addresses like that of Question 3. (5 pts)
9-bit 1 st-level page # 9-bit 2 nd-level page # 9-bit 3 rd-level page # 13-bit offset (Note other schemes will work as long as each page table requires less than 211 entries ( not 213 entries – remember 4 bytes per entry. )
6 Briefly enumerate the steps to resolve a virtual address to a physical address in your hierarchical paging scheme. (5 pts)
- 1 st^ 9 bits index into 1 st-level page table to find (base of ) 2 nd-level page table;
- 2 nd^ 9 bits index into 2 nd-level page table to find (base of) 3 rd-level page table;
- 3 rd^ 9 bits index into 3 rd-level page table to find (base of) physical frame;
- last 13 bits are offset of referenced memory in the physical frame.
7 Assuming actual memory access latency is 100 nanoseconds, without any caching, what is the effective memory access latency in your hierarchical scheme? (5 pts)
Effective memory access latency: 100 × 4 = 400 nanoseconds. (1 access for each of the three page tables, and 1 access for the requested memory.)
8 How might you integrate a TLB into your hierarchical paging scheme to reduce the effective memory access latency as much as possible? (A general description is sufficient.) (5 pts)
Any page table lookup that hits in the fast access TLB avoids a slow access to physical memory. The TLB should be used to cache entries from page tables at all levels of the page table hierarchy.
