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Lecture Notes Unit-1 & Unit-
Microprocessor and Microcontroller
Q. 1 List the features of 8086 Microprocessor. (i) The 8086 is a 16-bit microprocessor. (ii) The arithmetic logic unit and internal registers of 8086 Microprocessor are designed to work with 16-bit number. (iii) The 8086 Microprocessor has a 16-bit data bus, so it can read and write 16 – bit data from and to memory at a time. (iv) The 8086 Microprocessor has a 20-bit address bus, so it can directly access 1MB memory. (v) The 8086 Microprocessor provides fourteen 16-bit registers. (vi) The 8086 Microprocessor is packed as a 40 pin IC. (vii) The 8086 Microprocessor has multiplexed address and data bus which reduces the number of pins. (viii) There are three versions of 8086 Microprocessor and these are: 5 MHz for 8086 8 MHz for 8086- 2 10 MHz for 8086- 1 (ix) The different version of 8086 Microprocessor operates at different clock frequency as given below: 5 MHz for 8086 8 MHz for 8086- 2 10 MHz for 8086- 1 Q. 2 Explain the architecture of 8086 microprocessor.
The 8086 architecture divided into two units which works in parallel and these units are:
Function of BIU of 8086 microprocessor : (i) It generates 20 bit physical address for memory. (ii) It fetches instructions from memory. (iii) It reads data from memory or input device. (iv) It writes data into memory or output device. (v) It stores pre-fetched instructions in queue. Function of EU of 8086 microprocessor : (i) It decodes the fetched instruction. (ii) It generally provides the 16 bit offset address to BIU for the calculation of 20 bit physical address for memory. (iii) It performs arithmetic and logical operation. (iv) It executes the fetched instructions.
(ii) Interrupt Flag : This flag must be set to recognize maskable interrupt request at the INTR input of 8086. When this flag is reset, the requests at INTR are ignored. Trap Flag : If this flag is set then microprocessor enters in the single step execution mode. In other words, if this flag is set then trap interrupt is generated after the execution of each instruction. This mode of operation is used for debugging of software.
Q. 4 What is effective address and physical address? Calculate the physical address generated by 8086 microprocessor for the following cases: (i) CS = 2A40H & IP = AAAAH (ii) DS = 5D66H & BX = BCDEH
Answer Physical Address: The 20 bit address generated by 8086 microprocessor by using the content of segment register and offset address of data in a memory is called physical address. Effective Address: The distance of data from the base of a segment is called effective address or offset address. (i) Physical Address = (CS × 10H) + IP = (2A40H × 10H) + AAAAH = 2A400H + AAAAH = 34EAAH
(ii) Physical Address = (DS × 10H) + BX = (5D66H × 10H) + BCDEH = 5D660H + BCDEH = 6933EH
Q. 5 What do you mean by pipelining? How this concept is used in 8086? How many bytes can be stored in queue of 8086?
Answer Pipelining: Fetching the next instruction while the current instruction is executing is called pipelining. The concept of pipelining speed up the program execution. Pipelining is implemented in 8086 microprocessor by using a byte queue. Bus Interface Unit (BIU) of 8086 petches six instruction bytes ahead of time from the memory. These prefetched bytes are stored in the group of registers called queue. Now after finishing the decoding and execution of current instruction Execution Unit (EU) of 8086 fetches next instruction from queue rather than memory. In this way pipelining speed up the program execution. Q. 6 What is meant by memory segmentation? What are its advantages?
Answer Memory Segmentation: If a physical memory chip is divided into various logical parts then it is called as memory segmentation. In 8086 microprocessor maximum memory which can be connected to processor is 1 MB. By using memory segmentation this 1 MB memory is divided into number of logical Segments. Each of these segment is 64 Kb in size and addressed by one of the segment register. Advantages of Memory Segmentation: (i) It allows to address 1 MB memory by two 16 bit registers instead of a 20 bit register. (ii) It allows the programmer to put his program, data and stack in different areas of memory. (iii) It allows memory sharing by various users.
Q. 7 Explain the following: (i) Maskable interrupt and Non-maskable interrupt (ii) Vectored interrupt and non-vectored interrupt
Answer Maskable interrupt: The interrupt which can be disabled by using instruction is called maskable interrupt. Example is INTR Non-Maskable interrupt: The interrupt which can not be disabled by using instruction is called maskable interrupt. Example is NMI Vectored interrupt: The interrupt which transfer the sequence of a program to a fixed memory location without using external hardware is called vectored interrupt. NMI is an example of vectored interrupt. When interrupt NMI is activated then the sequence of a program is transferred to fixed memory location. The physical address of memory location where sequence of program is transferred is calculated from CS = 0000H and IP = 0008H. Non-Vectored interrupt: The interrupt which transfer the sequence of a program to a fixed memory location by using external hardware is called non-vectored interrupt. INTR is an example of non-vectored interrupt. When interrupt INTR is activated then the sequence of a program is transferred to fixed memory location by using an extra IC 8259. Q. 8 Explain the following address modes with example: (i) Register addressing mode (ii) Register indirect addressing mode (iii) Immediate addressing mode (iv) Direct addressing mode (v) Base Index Addressing Mode (vi) Relative Base Index Addressing Mode
Answer
(i) Register addressing mode: In this address mode the data is stored in a register and it is referred using the particular register. All registers except IP may be used in this mode. Examples (a) MOV BX, AX (b) MOV DL, AL (c) MOV SI, DX
Restrictions on the use of segment registers : (i) We may not specify CS as destination operand. For example, MOV CS, AX is not an valid instruction (ii) Only one operand can be segment register. We can not move data from one segment register to another segment register directly. For example, MOV DS, SS is an invalid instruction.
(ii) Register indirect addressing mode: In this addressing mode the offset address of the data is in any one of the register (base register or index register) BX, BP, SI OR DI.
Four forms of this addressing mode are : (a) MOV AL, [BX] (b) MOV AL, [BP] (c) MOV AL, [SI] (d) MOV AL, [DI]
Please note : (i) If the offset address is in [BP] then default segment of data is SS. (ii) If the offset address is in [BX], [SI] and [DI] then the default segment of data is DS.
(vi) Relative Base Index Addressing Mode: In this addressing mode the offset address of the data is calculated using 8-bit/16-bit relative value, base register (BX and BP) and index register (SI and DI).
Four forms of this addressing mode are: (a) MOV AL, 8-bit/16-bit relative value [BX][[SI] ; offset address of data is [8-bit/16-bit relative value + BX + SI] (b) MOV AL, 8-bit/16-bit relative value [BX][DI] ; offset address of data is [8-bit/16-bit relative value + BX + DI] (c) MOV AL, 8-bit/16-bit relative value [BP][SI] ; offset address of data is [8-bit/16-bit relative value + BP + SI] (d) MOV AL, 8 - bit/16-bit relative value [BP][DI] ; offset address of data is [8-bit/16-bit relative value + BP + DI] Please note: (i) If the base register BX is involved in an instruction then the default segment of data is DS. (ii) If the base register BP is involved in an instruction then the default segment of data is SS.
For example: MOV AL, 34H[BX][SI]. In above example data will be accessed from DS segment and offset address of data is [34H + BX
Q. 9 Explain the following instructions of 8086 microprocessor: (1) MOV (2) MOVSB (3) Loop ( 4 ) Call ( 5 ) RET (6) ADD (7) PUSH (8) POP ( 9 ) CMP ( 10 ) XCHG (11) ROL ( 12 ) RCL (13) ROR (14) RCR (15) AND (16) OR (17) XOR (18) NOT
Answer (1) MOV: MOV instruction is used to transfer data from registers/memory.
Example (i) MOV AL, BL
8 - bit data is transferred from register BL to AL (ii)) MOV AX, CX 16 - bit data is transferred from register CX to AX
(iii) MOV AL, [SI] 8 - bit data from memory is transferred to AL. The offset address of data is stored in SI. (2) MOVSB: It is an example of string instruction. A string is a series of numbers stored in consecutive memory locations.
MOVSB instruction moves a string of 8-bit numbers from DS:SI to ES:DI CX number of times.
( 3 ) LOOP: This instruction decrements the content of sixteen bit register CX by 1 and if value of CX is not zero the program sequence is transferred to the LABEL written after LOOP instruction.
If the content of CX becomes zero then program will comes out the LOOP and next instruction
written after LOOP is executed.
( 4 ) CALL: (a) This instruction is used to transfer the sequence of execution from main program
to subroutine (procedure).
(b) When CALL instruction is executed then processor stores the address of next instruction of
CALL into stack and then processor will go to execute the instructions of subroutine.
(c) Last instruction of subroutine must be RET (return).
(d) When processor executes RET instruction then the address stored in stack will be popped
up and processor will go to next instruction of CALL for execution.
( 5 ) RET: (a) This instruction is used to transfer the sequence of execution from subroutine
(procedure) to main program.
(b) When CALL instruction is executed then processor stores the address of next instruction of
CALL into stack and then processor will go to execute the instructions of subroutine.
(c) Last instruction of subroutine must be RET (return).
(d) When processor executes RET instruction then the address stored in stack will be popped
up and processor will go to next instruction of CALL for execution.
( 6 ) ADD: In ADD AL, 56H a 8 bit number 56H is added with the content of AL and result will be
placed in AL.
(a) In ADD AX, 5678H a 16 bit number 5678H is added with the content of AX. 56H is added
with the content of AH and 78H is added with the content of AL. The result after addition will be
placed in AX.
(b) In ADD AL, [BX] a 8 bit number whose offset address is given by BX register is added with
the content of AL and result will be placed in AL.
( 7 ) PUSH: The PUSH instruction is used to transfer the content of registers in stack segment
memory area.
For example PUSH AX instruction transfers the content of AH register in stack segment
memory area at offset address [SP – 1] and the content of AL register at [SP – 2] offset address.
Here, SP is Stack Pointer register points the stack top memory location. After the execution of
PUSH AX the new value of SP is [SP – 2].
Example:
Let AX = 5346H and SP = FFFFH then after the execution of PUSH AX the content of AH (i.e 53H)
will be loaded at offset address FFFEH of stack segment and the content of AL (i.e 46H) will be
shifted left.
Example-1: ROL AL,01H
Explanation – The content of AL is rotated left side by one bit. The MSB bit of AL is send to carry
flag and at LSB position.
Example-2: ROL AL,CL
Explanation – The content of AL is rotated left side by CL number of times. If we want to rotate
the value of register more than one times then that value must be loaded in CL register.
(12) RCL: RCL instruction rotates the content of a 8-bit/16-bit register left side by n number of
times. The MSB bit goes inside Carry flag and carry flag bit goes to LSB position and all the bits
of register shifted left.
Example-1: RCL AL,01H
Explanation – The content of AL is rotated left side by one bit through carry flag. The MSB bit of
AL is send to carry flag and carry flag bit goes to LSB position.
Example-2: RCL AL,CL
Explanation – The content of AL is rotated left side by CL number of times. If we want to rotate
the value of register more than one times then that value must be loaded in CL register.
(13) ROR: ROR instruction rotates the content of a 8-bit/16-bit register right side by n number
of times. The LSB bit go inside Carry flag as well as at MSB position and all the bits of register
shifted right.
Example-1: ROR AL,01H
Explanation – The content of AL is rotated right side by one bit. The LSB bit of AL is send to
carry flag and at MSB position.
Example-2: ROL AL,CL
Explanation – The content of AL is rotated right side by CL number of times. If we want to rotate
the value of register more than one times then that value must be loaded in CL register.
(14) RCR: RCR instruction rotates the content of a 8-bit/16-bit register right side by n number
of times. The LSB bit go inside Carry flag and carry flag bit goes to MSB position and all the bits
of register shifted right.
Example-1: RCR AL,01H
Explanation – The content of AL is rotated right side by one bit. The LSB bit of AL is send to
carry flag and carry flag bit goes to MSB position and all the bits of register shifted right once.
Example-2: RCR AL,CL
Explanation – The content of AL is rotated right side by CL number of times. If we want to rotate
the value of register more than one times then that value must be loaded in CL register.
(15) AND d, s
AND operation is performed on all the bits of destination and source and the result is stored in
d.
Example-1: AND AL,0FH
Explanation – The content of AL is ANDed with 0FH and result will be stored in AL.
Let AL=FFH, after the execution of AND AL,0FH instruction the result is 0FH and stored in AL.
(16) OR d, s
OR operation is performed on all the bits of destination and source and the result is stored in d.
Example-1: OR AL,0FH
Explanation – The content of AL is ORed with 0FH and result will be stored in AL.
Let AL=FFH, after the execution of OR AL,0FH instruction the result is FFH and stored in AL.
(17) XOR d, s
XOR operation is performed on all the bits of destination and source and the result is stored in
d.
Q. 1 2 Explain the function of following signals of 8086 microprocessors:
(i) MN/MX’ (ii) ALE (iii) DEN’ (iv) DT/R’ (v) M/IO’ (vi) RD’ (vii) WR’ (viii) NMI (ix) INTR (x) INTA’ (xi) HOLD (xii) HLDA (xiii) Ready (xiv) Test’ (xv) Reset (xvi) AD 15 to AD 0 (xvii) A 16 /S 3 to AD 19 /S 6
Answer
(i) MN / MX’: (a) 8086 microprocessor can work in two modes i.e Minimum mode and Maximum mode. (b) If we are using single microprocessor then it works in Minimum mode. (c) If we are using two or more microprocessors then it works in Maximum mode. (d) MN / MX’ pin of 8086 is used to select Minimum mode and Maximum mode of processor. (e) If MN / MX’=0 then 8086 processor works in Maximum mode. (f) If MN / MX’=1 then 8086 processor works in Minimum mode.
(ii) ALE:
(a) ALE (Address Latch Enable) (b) This is the output signal generated by microprocessor. (c) This signal goes HIGH during T-1 and remains LOW during the whole machine cycle. ALE is used to demultiplex AD15 – AD0 into A15 – A0 and D15 – D0. (d) It also demultiplex higher four address lines and status signals. (e) ALE connected to CLOCK input of latch IC (74LS373).
(iii) DEN’:
(a) DEN’ (Data Enable’) (b) This is the output signal generated by microprocessor. (c) DEN’ connected to ENABLE pin of octal transreceiver IC (74LS245). (d) A LOW on DEN’ enables octal transreceiver IC (74LS245) and microprocessor can send and receive data.
(iv) DT / R’: (a) (Data Transmit/ Receive’) (b) This is the output signal generated by microprocessor. (c) DT/R’ connected to DIRECTION CONTROL pin of octal transreceiver IC (74LS245). (d) A LOW on DT/R’ indicates that microprocessor is going to receive data for read operation. (e) A HIGH on DT/R’ indicates that microprocessor is going to send (transmit) data for write operation.
(v) M/IO’:
(a) This is the output signal generated by microprocessor. (b) This signal indicates whether 8086 microprocessor is interaction with memory of IO device. (c) If M/IO’=0 then 8086 processor interact with IO devices. (d) If M/IO’=1 then 8086 processor interact with memory devices.
(vi) RD’ (Read’): (a) This is the output signal generated by microprocessor. (b) When microprocessor reads data from memory or input device then RD’ goes low.
(vii) WR’ (Write’): (a) This is the output signal generated by microprocessor. (b) When microprocessor writes data in memory or output device then WR’ goes low.
(viii) NMI (Non Maskable Interrupt):
(ix) INTR (Interrupt)
(x) INTA’ (Interrupt Acknowledge)
(xi) HOLD
(xii) HLDA
(xiii) Ready
Explanation of various signals associated with Memory Read Cycle:
(i) M/IO’:
This is the output signal generated by microprocessor. This signal goes HIGH during T-1 state and remains HIGH during whole machine cycle. It to indicate that this is memory related operation.
(ii) ALE (Address Latch Enable):
This is the output signal generated by microprocessor. This signal goes HIGH during T-1 and remains LOW during the whole machine cycle. ALE is used to demultiplex AD15 – AD0 into A15 – A0 and D15 – D0. It also demultiplex higher four address lines and status signals. ALE connected to CLOCK input of latch IC (74LS373).
(iii) DT/R’ (Data Transmit/ Receive’):
This is the output signal generated by microprocessor. This signal goes LOW during T-1 and remains LOW during the whole machine cycle. DT/R’ connected to DIRECTION CONTROL pin of octal transreceiver IC (74LS245). A LOW on DT/R’ indicates that microprocessor is going to receive data for read operation.
(iv) DEN’ (Data Enable’):
This is the output signal generated by microprocessor. This signal goes LOW during T-2 and remains LOW during the whole machine cycle. DEN’ connected to ENABLE pin of octal transreceiver IC (74LS245). A LOW on DEN’ enables octal transreceiver IC (74LS245).
(iv) RD’ (Read’):
This is the output signal generated by microprocessor. This signal goes LOW during T-2 and remains LOW during the whole machine cycle. A LOW on RD’ along with HIGH on M/IO’ enables read operation from RAM/ROM.
(iv) WR’ (Write’):
This is the output signal generated by microprocessor. This signal remains HIGH during the whole machine cycle.
(v) AD15 – AD0:
Microprocessor sends the lower 16 bits of address of memory from where it wants to read the data on AD15 – AD0 lines during T-1 state. During the end of T-2 state data from memory will come on AD15 – AD0 line.
(vi) A16/S3 – A19/S6:
Microprocessor sends the higher 4 bits of address of memory from where it wants to read the data on A16/S3 – A19/S6 lines during T-1 state. During the T-2 status from S3 – S6 will be available on A16/S3 – A19/ S6 lines.
Q. 1 4 Analyze the effect on various signals at different T states during memory write cycle in minimum mode of operation of 8086 microprocessor.
Explanation of various signals associated with Memory Write Cycle:
(i) M/IO’: This is the output signal generated by microprocessor. This signal goes HIGH during T-1 state and remains HIGH during whole machine cycle. It to indicate that this is memory related operation.
(ii) ALE (Address Latch Enable): This is the output signal generated by microprocessor. This signal goes HIGH during T-1 and remains LOW during the whole machine cycle. ALE is used to demultiplex AD15 – AD0 into A15 – A0 and D15 – D0. It also demultiplex higher four address lines and status signals. ALE connected to CLOCK input of latch IC (74LS373).
(iii) DT/R’ (Data Transmit/ Receive’): This is the output signal generated by microprocessor. This signal goes HIGH during T-1 and remains HIGH during the whole machine cycle. DT/R’ connected to DIRECTION CONTROL pin of octal transreceiver IC (74LS245). A HIGH on DT/R’ indicates that microprocessor is going to transmit data for write operation.
MACRO:
(a) Macro is also group of instructions written to perform some specific task, (b) Directive to create macro: Name_of_macro MACRO Macro is ended by ENDM. (c) Whenever we need macro we write “Name_of_macro” while writing program. When program is assembled then in place of macro the code of macro is inserted in program. (d) When macro is used in program then size of program increases as compare to procedure. (e) When macro is used in program then the execution of program is fast as compare to procedure. (f) Macro does not use stack.
Q. 20 1) Interface 64K Х 8 EPROM and 64K Х 8 RAM chips with 8086 microprocessor. During
memory mapping ensure that the starting address of RAM is 00000H and the address
FFFF0H must lies in EPROM. Indicate the last location in EPROM and RAM chips.
Ans: Interface 64K Х 8 EPROM
- 16 Address lines are required [A0 – A15] - Two chips of 32K × 8 EPROM are required. One chip will acts as EVEN bank and other chip will acts as ODD bank.
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range of 64K × 8 EPROM = FFFFF H – F0000 H
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Interface 64K Х 8 RAM
- 16 Address lines are required [A0 – A15] - Two chips of 32K × 8 RAM are required. One chip will acts as EVEN bank and other chip will acts as ODD bank. -
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range of 64K × 8 RAM = 00000 H – 0FFFF H
Last location in EPROM is FFFFF H & Last location in RAM is 0FFFF H
Interfacing diagram:
Q. 21 Interface 32K Х 8 EPROM and 32K Х 8 RAM chips with 8086 microprocessor. During memory mapping ensure that the starting address of RAM is 00000H and the address FFFF0H must lies in EPROM. Indicate the last location in EPROM and RAM chips. Solution: Interface 32K Х 8 EPROM 15 Address lines are required [A0 – A14] Two chips of 16K × 8 EPROM are required. One chip will acts as EVEN bank and other chip will acts as ODD bank.
