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UNIT I
FUNDAMENTALS OF COMPUTER DESIGN
Introduction
Today’ s desktop computers (less than $500 cost) ar e having more performance, larger memory and storage than a computer bought in 1085 for 1 million dollar. Highest performance microprocessors of today outperform Supercomputers of less than 10 years ago. The rapid improvement has come both from advances in the technology used to build computers and innovations made in the computer design or in other words, the improvement made in the computers can be attributed to innovations of technology and architecture design.
During the first 25 years of electronic computers, both forces made a major contribution, delivering performance improvement of about 25% per year. Microprocessors were evolved during late 1970s and their ability along with improvements made in the Integrated Circuit (IC) technology y contributed to 35% performance growth per year.
The virtual elimination of assembly language programming reduced the n eed for object-code compatibility. The creation of standardized vendor-independent operating system lowered the cost and risk of bringing out a new architecture.
In the yearly 1980s, the Reduced Instruction Set Computer (RISC) based machines focused the attention of designers on two critical performance techniques, the exploitation Instruction Level Parallelism (ILP) and the use of caches. The figu re 1.1 shows the growth in processor performance since the mid 1980s. The graph plots performance relative to the VAX-11/780 as measured b y the SPECint benchmarks. From the figure it is clear that architectural and organizational enhancements led to 16 years of sustained growth in performance at an annual rate of over 50%. Since 2002, processor performance improvement has dropped to about 20% per year due to the following hurdles:
•Maximum power dissipation of air-cooled chips •Little ILP left to exploit efficiently •Limitations laid by memory latency
The hurdles signals historic switch from relying solely on ILP to Thread Level Parallelism (TLP) and Data Level Parallelism (DLP).
Figure 1.1 The evolution of various classes of computers:
Classes of Computers
1960 : Large Main frames (Millions of $ ) (Applications: Business Data processing, large Scientific computin g) 1970: Minicomputers (Scientific laboratories, Time sharing concepts) 1980: Desktop Computers (μPs) in the form of Personal computers and workstations. (Larger Memory, more computing power, Replaced Time sharing g systems) 1990: Emergence of Internet and WWW, PDAs, emergence of high performance digital consumer electronics 2000: Cell phones These changes in computer use have led to three different computing classes each characterized by different applications, requirements and computing technologies.owth in processor performance since 1980s
Defining C omputer Arch itecture The computer designer has to ascertain the attributes that are important for a new computer and design the system to maximize the performance while staying within cost, power and availability constraints. The task has few important aspects such as Instruction Set design, Functional organization, Logic design and implementation.
Instruction Set Architecture (ISA)
ISA refers to the actual programmer visible Instruction set. The ISA serves as boundary between the software and hardware. Th e seven dimensions of the ISA are:
i)Class of ISA : Nearly all ISAs today ar e classified as General-Purpose- Register architectures. The operands are either Registers or Memory locations. The two popular versions of this class are: Register-Memory ISAs : ISA of 80x86, can access memory as part of many instructions. Load -Store ISA Eg. ISA of MIPS, can access memory only with Load or Store instructions.
ii) Memory addressing : Byte addressing scheme is most widely used in all desktop and server computers. Both 80x86 and MIPS use byte addressing. Incase of MIPS the object must be aligned. An access to an object of s b yte at byte address A is aligned if A mod s =0. 80x86 does not require alignment. Accesses are faster if operands are aligned.
iii) Addressing modes :Specify the address of a M object apart from register and constant operands. MIPS Addressing modes: •Register mode addressing •Immediate mode addressing •Displacement mode addressing 80x86 in addition to the above addressing modes supports the additional modes of addressing: i. Register Indirect ii. Indexed iii,Based with Scaled index
iv)Types and sizes of operands: MIPS and x86 support: •8 bit (ASCII character), 16 bit(Unicode character) •32 bit (Integer/word ) •64 bit (long integer/ Double word) •32 bit (IEEE-754 floating point) •64 bit (Double precision floating point) •80x86 also supports 80 bit floating point operand.(extended double Precision
v)Operations :The general category o f operations are: oData Transfer oArithmetic operations oLogic operations oControl operations oMIPS ISA: simple & easy to implement ox86 ISA: richer & larger set of operations
vi) Control flow instructions :All ISAs support: Conditional & Unconditional Branches Procedure C alls & Returns MIPS 80x
- Conditional Branches tests content of Register Condition code bits
- Procedure C all JAL CALLF
- Return Address in a R Stack in M
vii) Encoding an ISA Fixed Length ISA Variable Length ISA MIPS 32 Bit long 80x86 (1-18 bytes) Simplifies decoding Takes less space
Number of Registers and number of Addressing modes hav e significant impact on the length of instruction as the register field and addressing mode field can appear many times in a single instruction.
Trends in Technology
The designer must be aware of the following rapid changes in implementation technology. •Integrated C ircuit (IC) Logic technology •Memory technology (semiconductor DRAM technology) •Storage o r magnetic disk technology •Network technology
IC Logic technology:
Transistor density increases by about 35%per year. Increase in die size corresponds to about 10 % to 20% per year. The combined effect is a growth rate in transistor count on a chip of about 40% to 55% per year. Semiconductor DRAM technology:cap acity increases by about 40% per year. Storage Technology: Before 1990: the storage density increased by about 30% per year. After 1990: the storage density increased by about 60 % per year. Disks are still 50 to 100 times cheaper per bit than DRAM.
•Transistor count improves quadratically with a linear improvement in Transistor performance. •!!! Wire delay scales poo rly comp ared to Transistor performance. •Feature sizes shrink, wires get shorter. •Signal delay fo r a wire increases in proportion to the product of Resistance and Capacitance.
Trends in Power in Integrated Circuits
For CMOS chips, the dominant source of energy consumption is due to switching transistor, also called as Dynamic power and is given b y the following equation.
Power = (1/2)Capacitive load Voltage**
- Frequency switched dynamic •For mobile devices, energy is the better metric
Energy dynamic = Capacitive load x Voltage 2
•For a fix ed task, slowing clock rate (frequency switched) reduces power, but not energy •Capacitive load a function of number of transistors connected to output and technology, which determines capacitance of wires and transistors
•Dropping voltage helps both, so went from 5V down to 1V •To save energy & dynamic power, most CPUs now turn off clock of inactive modules •Distributing the power, removing the heat and preventing hot spots have become increasingly difficult challenges.
- The leakage current flows even when a transistor is off. Therefore static power is equally important.
Power static= Current static * Voltage
•Leakage current increases in processors with smaller transistor sizes •Increasing the number of transistors increases power even if they are turned off •In 2006, goal for leakage is 25% of total power consumption; high performance designs at 40% •Very low power systems even gate voltage to inactive modules to control loss due to leakage
Trends in Cost
- The underlying principle that drives the cost down is the learning curvemanufacturing costs decrease over time.
- Volume is a second key factor in determining cost. Volume decreases cost since it increases purchasing manufacturing efficiency. As a rule of thumb, the cost decreases
about 10% for each doubling of volume.
- Cost of an Integrated Circuit Although the cost of ICs have dropped exponentially, the basic process of silicon manufacture is unchanged. A wafer is still tested and chopped into dies that are packaged.
Cost of IC = Cost of [die+ testing die+ Packaging and final test] / (Final test yoeld)
Cost of die = Cost of wafer/ (Die per wafer x Die yield)
The number of dies per wafer is approximately the area of the wafer divided by the area of the die.
Die per wafer = [_ * (Wafer Dia/2)2/Die area]-[* wafer dia/(2*Die area)]
The first term is the ratio of wafer area to die area and the second term compensates for the rectangular dies near the periphery of round wafers(as shown in figure).
Dependability:
The Infrastructure providers offer Service Level Agreement (SLA) or Service Level Objectives (SLO) to guarantee that their networking or power services would be dependable.
Benchmarks
The real applications are the best choice of benchmarks to evaluate the performance. However, for many of the cases, the workloads will not be known at the time of evaluation. Hence, the benchmark program which resemble the real applications are chosen. The three types of benchmarks are:
- KERNELS, which are small, key pieces of real applications;
- Toy Programs: which are 100 line programs from beginning programming assignments, such Quicksort etc.,
- Synthetic Benchmarks: Fake programs invented to try to match the profile and behavior of real applications such as Dhrystone. To make the process of evaluation a fair justice, the following points are to be followed.
- Source code modifications are not allowed.
- Source code modifications are allowed, but are essentially impossible.
- Source code modifications are allowed, as long as the modified version produces the same output.
- To increase predictability, collections of benchmark applications, called benchmark suites , are popular
- SPECCPU: popular desktop benchmark suite given by Standard Performance Evaluation committee (SPEC)
- CPU only, split between integer and floating point programs
- SPECint2000 has 12 integer, SPECfp2000 has 14 integer programs
- SPECCPU2006 announced in Spring 2006. SPECSFS (NFS file server) and SPECWeb (WebServer) added as server benchmarks
- Transaction Processing Council measures server performance and costperformance for databases
- TPC-C Complex query for Online Transaction Processing
- TPC-H models ad hoc decision support
- TPC-W a transactional web benchmark
- TPC-App application server and web services benchmark
- SPEC Ratio: Normalize execution times to reference computer, yielding a ratio proportional to performance = time on reference computer/time on computer being rated
- If program SPECRatio on Computer A is 1.25 times bigger than Computer B, then
- Note : when comparing 2 computers as a ratio, execution times on the reference computer drop out, so choice of reference computer is irrelevant.
Quantitative Principles of Computer Design
While designing the computer, the advantage of the following points can be exploited to enhance the performance.
- Parallelism: is one of most important methods for improving performance.
- One of the simplest ways to do this is through pipelining ie, to over lap the instruction Execution to reduce the total time to complete an instruction sequence.
- Parallelism can also be exploited at the level of detailed digital design.
- Set- associative caches use multiple banks of memory that are typically searched n parallel. Carry look ahead which uses parallelism to speed the process of computing.
Principle of locality: program tends to reuse data and instructions they have used recently. The rule of thumb is that program spends 90 % of its execution time in only 10% of the code. With reasonable good accuracy, prediction can be made to find what instruction and data the program will use in the near future based on its accesses in the recent past.
Focus on the common case while making a design trade off, favor the frequent case over the infrequent case. This principle applies when determining how to spend resources, since the impact of the improvement is higher if the occurrence is frequent.
Amdahl’s Law: Amdahl’s law is used to find the performance gain that can be obtained by improving some portion or a functional unit of a computer Amdahl’s law defines the speedup that can be gained by using a particular feature. Speedup is the ratio of performance for entire task without using the enhancement when possible to the performance for entire task without using the enhancement. Execution time is the reciprocal of performance. Alternatively, speedup is defined as thee ratio of execution time for entire task without using the enhancement to the execution time for entair task using the enhancement when possible. Speedup from some enhancement depends an two factors:
Example:
A System contains Floating point (FP) and Floating Point Square Root (FPSQR) unit. FPSQR is responsible for 20% of the execution time. One proposal is to enhance the FPSQR hardware and speedup this operation by a factor of 15 second alternate is just to try to make all FP instructions run faster by a factor of 1.6 times faster with the same effort as required for the fast FPSQR, compare the two design alternative
UNIT II
Pipelining: Basic and Intermediate concepts
Pipeline is an implementation technique that exploits parallelism among the instructions in a sequential instruction stream. Pipeline allows to overlapping the execution of multiple instructions. A Pipeline is like an assembly line each step or pipeline stage completes a part of an instructions. Each stage of the pipeline will be operating an a separate instruction. Instructions enter at one end progress through the stage and exit at the other end. If the stages are perfectly balance. (assuming ideal conditions), then the time per instruction on the pipeline processor is given by the ratio:
Time per instruction on unpipelined machine/ Number of Pipeline stages
Under these conditions, the speedup from pipelining is equal to the number of stage pipeline. In practice, the pipeline stages are not perfectly balanced and pipeline does involve some overhead. Therefore, the speedup will be always then practically less than the number of stages of the pipeline. Pipeline yields a reduction in the average execution time per instruction. If the processor is assumed to take one (long) clock cycle per instruction, then pipelining decrease the clock cycle time. If the processor is assumed to take multiple CPI, then pipelining will aid to reduce the CPI.
A Simple implementation of a RISC instruction set Instruction set of implementation in RISC takes at most 5 cycles without pipelining. The 5 clock cycles are:
1. Instruction fetch (IF) cycle: Send the content of program count (PC) to memory and fetch the current instruction from memory to update the PC. 2. Instruction decode / Register fetch cycle (ID):
Decode the instruction and access the register file. Decoding is done in parallel with reading registers, which is possible because the register specifies are at a fixed location in a RISC architecture. This corresponds to fixed field decoding. In addition it involves:
- Perform equality test on the register as they are read for a possible branch.
- Sign-extend the offset field of the instruction in case it is needed.
- Compute the possible branch target address.
Each stage of the pipeline must be independent of the other stages. Also, two different operations can’t be performed with the same data path resource on the same clock. For example, a single ALU cannot be used to compute the effective address and perform a subtract operation during the same clock cycle. An adder is to be provided in the stage 1 to compute new PC value and an ALU in the stage 3 to perform the arithmetic indicatedin the instruction (See figure 2.2). Conflict should not arise out of overlap of instructions using pipeline. In other words, functional unit of each stage need to be independent of other functional unit. There are three observations due to which the risk of conflict is reduced.
- Separate Instruction and data memories at the level of L1 cache eliminates a conflict for a single memory that would arise between instruction fetch and data access.
- Register file is accessed during two stages namely ID stage WB. Hardware should allow to perform maximum two reads one write every clock cycle.
- To start a new instruction every cycle, it is necessary to increment and store the PC every cycle.
Buffers or registers are introduced between successive stages of the pipeline so that at the end of a clock cycle the results from one stage are stored into a register (see figure 2.3). During the next clock cycle, the next stage will use the content of these buffers as input. Figure 2.4 visualizes the pipeline activity.
Pipeline Hazards
Hazards may cause the pipeline to stall. When an instruction is stalled, all the instructions issued later than the stalled instructions are also stalled. Instructions issued earlier than the stalled instructions will continue in a normal way. No new instructions are fetched during the stall. Hazard is situation that prevents the next instruction in the instruction stream fromk executing during its designated clock cycle. Hazards will reduce the pipeline performance.
Performance with Pipeline stall
A stall causes the pipeline performance to degrade from ideal performance. Performance improvement from pipelining is obtained from:
Assume that, i) cycle time overhead of pipeline is ignored ii) stages are balanced With theses assumptions
If all the instructions take the same number of cycles and is equal to the number of pipeline stages or depth of the pipeline, then,
If there are no pipeline stalls, Pipeline stall cycles per instruction = zero Therefore, Speedup = Depth of the pipeline.
Types of hazard Three types hazards are:
- Structural hazard
- Data Hazard
- Control Hazard
Structural hazard
Structural hazard arise from resource conflicts, when the hardware cannot support all possible combination of instructions simultaneously in overlapped execution. If some combination of instructions cannot be accommodated because of resource conflicts, the processor is said to have structural hazard. Structural hazard will arise when some functional unit is not fully pipelined or when some resource has not been duplicated enough to allow all combination of instructions in the pipeline to execute. For example, if memory is shared for data and instruction as a result, when an instruction contains data memory reference, it will conflict with the instruction reference for a later instruction (as shown in figure 2.5a). This will cause hazard and pipeline stalls for 1 clock cycle.
