ECE 6050 ADVANCED MICROPROCESSOR APPLICATIONS
Summer II 2009
Project Assignment #2
Team Project
Total: 100 pts. (25% of course grade)
Due 6:30pm, Wednesday, July 22, 2009
Design a dual port, 16MB 32-bit SDRAM memory block along with its controller (referred to as
SDRAMC) such that one of the memory ports will be interfaced to the MPC563 Bus. Your design
should seamlessly integrate with circuits developed in Project #1. In addition, develop a hardware
emulator for the MPC563 Bus along with single-stepping capability for debug and verification
purposes using a Nexys 2 Board.
The other memory port will be interfaced to the VME64x Bus in Project #3. A functional block
diagram for this project is given on the next page. The schematic diagram should include the
following:
- the SDRAM memory block such that only one SDRAM chip is given in full detail
- a rectangular representing the Vertex 2 Pro chip that implements the SDRAMC and other
necessary circuits for the SDRAM block
- parts external to the Vertex 2 Pro chip and the memory chips (if any)
Micron MT48LC32M8A2TG-6A chips are assigned to implement the SDRAM memory block.
The dual port access to the SDRAM block should be implemented by using TS Transceivers and
Buffers mapped to the Vertex 2 Pro chip. The required refresh rate is 64ms for all 8192 rows, and
automatic refresh cycles should be used for all SDRAM chips.
The core of the SDRAMC will be a synchronous state machine to deal with the timing issues of
your design. You may assume that a 100MHz (50 % duty cycle) clock generator (asynchronous
with respect to the MPC563 CPU clock) is available as a timing reference.
For the MPC563 Bus hardware emulator you should establish a 25MHz CLKOUT signal. Use the
Hirose connector on the Nexys 2 Board to implement the bus signals. By analyzing the performance
of your SDRAM memory unit you should make a decision with respect to the necessary number of
wait states on the MPC563 Bus and assert the proper input of the wait state generator circuit for
Project #1.
Tasks:
1. Develop VHDL programs to emulate a suitable set of MPC563 bus cycles in order to
verify the correct operation of your SDRAM memory module. Provide for single-step
capability. Implement this MPC563 bus emulator using a Nexys 2 Board.
