Download Digital Logic Terms: Clocking, Systems, Flip-Flops, Latches, D Flip-Flops, Setup/Hold Time and more Quizzes Computer Architecture and Organization in PDF only on Docsity!
Edge Triggered Clocking
A clocking scheme in which all state changes occur on a clock edge. TERM 2
synchronous system
DEFINITION 2 A memory system that employs clocks and where data signals are read only when the clock indicates that the signal values are stable. TERM 3
flip-flop
DEFINITION 3 A memory element for which the output is equal to the value of the stored state inside the element and for which the internal state is changed only on a clock edge. TERM 4
latch
DEFINITION 4 A memory element in which the output is equal to the value of the stored state inside the element and the state is changed whenever the appropriate inputs change and the clock is asserted. TERM 5
D flip-
flop
DEFINITION 5 A flip-flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs.
setup time
The minimum time that the input to a memory device must be valid before the clock edge. TERM 7
hold time
DEFINITION 7 The minimum time during which the input must be valid after the clock edge. TERM 8
combinational logic
DEFINITION 8 A logicsystem whose blocks do notcontain memory and hencecompute the same output giventhe same input. TERM 9
sequential logic
DEFINITION 9 A group oflogic elements that containmemory and hence whose valuedepends on the inputs as well asthe current contents of thememory. TERM 10
gate
DEFINITION 10 A device that implementsbasic logic functions, such asAND or OR.
read-only memory (ROM)
Amemory whose contents aredesignated at creation time,after which the contents canonly be read. ROM is used asstructured logic to implement aset of logic functions by usingthe terms in the logic functionsas address inputs and the outputs as bits in each word of thememory. TERM 17
programmable ROM (PROM)
DEFINITION 17 A form of read-onlymemory that can be programmed when a designerknows its contents. TERM 18
bus
DEFINITION 18 In logic design, a collectionof data lines that is treatedtogether as a single logical signal. TERM 19
clock skew
DEFINITION 19 The difference inabsolute time between the timeswhen two state elements see aclock edge
