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What is the main differ- ence between Intel and ARM processor
What do ARM instructions only operate on
What is the model used by ARM for memory access
If we were to increment a 32-bit value at a particu- lar memory address, how many types of instructions would we need
The instruction set. Intel is a CISC (complex in- struction set computing) processor - ARM is a RISC (reduced), more general purpose registers
Registers
Load/Store
3 - ARM uses load/store memory model, so uses load, increment and store. First load value at particu- lar address into a register, increment it within the reg- ister, and store it back to the memory address from the register.
Instruction execution is quicker (fewer clock cycles per instruction).
Disadv:
Name one advantage and disadvantage a reduced instruction set (RISC) has
Describe the endianness of ARM
What capability do most ARM instructions have (to do with branching etc)
What is the tool used to assemble assembly code into machine code Since we cant remember the binary patterns of ma- chine code instructions, what do we use Where do the operands come in an instruction
What are the data types we can load or store, and what are their exetensions
What do the following in- structions do:
Greater emphasis on the efficient writing of soft- ware with limited instruc- tions available Its bi-endian, allows for switchable endianness
Conditional execution
GNU Assembler
Mnemonics - where each machine code instruction is given a name.
After the mnemonic(s)
Halfwords (-h or -sh) Bytes (-b or -sb) Words (no extension)
What is the endianness of ARM. What is this con- trolled by
Generally speaking, how many general registers are there in ARM. How big are they
The first 16 general pru- pose registers are accessi- ble in mode
When are the additional registers accessible. What registers are we looking at in this course?
What is the purpose of the registers R0-R
What is the purpose of the register R
What is the purpose of the registers R8-
tle-endian and data ac- cesses can be either LE or BE. This is controlled by bit 9, the E-bit, of the Program Status Register (CPSR)
30 general purpose 32-bit registers
User-level mode
Privileged software execu- tions.
We are working with regis- ters that are accessible in privilege mode, r0-r
What is the purpose of the register R
What is the purpose of the register R
What is the purpose of the register R
What is the purpose of the register R
What is the purpose of the register R
What is the last register called
Out of the 16 addition- al registers in privilege mode, what registers are general purpose registers, and what are special pur- pose registers
General purpose Holds syscall number General Purpose Frame Pointer (FP) Intra proceduaral cell (IP) Stack Pointer (SP) Link register (LR) Program Counter (PC)
Current program status register (CPSR)
General: R0-R Special: R12-R16 (and CPSR)
What is a stack
What does R14 do
An area of memory used for function-specific stor- age, which is reclaimed when function returns Link Register When a function call is made, LR gets updated with a memory address referencing the next instr- ruction where the func- tion was initiated from. This allows the program to return to the "parent" function that initiated the "child" function call after the "child" function is fin- ished
What does R15 do
What happens during a branch insturction with R
How large is an ARM in- struction
If the address of the in- struction: MOV r0, pc
Program Counter
- the PC is automatically incrmeented by the size of the instruction executed ( bytes)
When branch instruction executed, PC holds des- tination address. During execution, PC stores ad- dress of the current in- struction plus 8 (2 ARM in- structions)
Note, in x86, PC always points to next instruction being executed.
4 bytes
Initially, PC would hold the address 0x8054 (the next instruction to be executed). After executing the instruc- tion, R0 holds the address of PC (0x8054) + 2 in-
Name the main flags in the CPSR register
What about the others
What are the bits used for in CPSR
What cells in CPSR are size of one bit
When is C enabled in CPSR When is V enabled in CPSR
Negative, Zero, Carry, Overflow, Interrupt, Fast Thumb.
Underflow, Jazelle, GE (greater than or equal), En- dianness, Abort disable, IRQ disable, FIQ disable, Privielege mode
To support conditional ex- ecution in conditionals and loops at the assembly level All of them apart from GE and M
(Carry): Enabled if result of instruction yields a value that needs a 33rd bit to be fully represented. Also, if the result of a subtraction is positive or zero
(oVerflow): Enabled if re-
When is E enabled in CPSR
If we CMP 2 equal num- bers, what is the Zero flag set to
If we CMP 1, 2. What is the zero flag set to, what about N flag
If we CMP R1, R0 and r holds 2 and r1 holds 4, what flag is enabled
When does a carry occur (C = 1)
sult of instruction yields a value that cant be repre- sented in 32 bit 2s comp
(endianness): 0 for LE, 1 for BE
Z = 1
Z = 0, N = 1 (1 - 2 = -1)
Therefore Carry flag is set.
If result of addition is greater than or equal to 2^
If result of a subtraction is positive or zero
The result of an inline bar- rel shifter operation in a
What is the general tem- plate for ARM instructions
Normally one or two operands..
Mnemonics - short name of instruction
{S} - optional suffix, if spec- ified, condition flags are updated on the result of operation
{condition} - condition needed for instruction to be executed
{Rd} - register destination for storing result of opera- tion
Operand 1 - first op, either a register or immediate val- ue
Operand 2 - second, flex- ible, operand, can be im-
Why is Operand 2 flexible
What do the following ex- pressions for Operand 2 do:
Rx, ASR n Rx, LSL n
What does this instruction do
ADD R0, R1, R
What does this instruction do
ADD R0, R1,
What does this instruction do
Can use it in various forms, immediate value, register, or register with a shift Register x with arithmetic shift right by n bits (1 = n = 32)
Register x with logical shift left by n bits (1 = n = 32) adds contents of r (operand1) and r (operand 2 in the form of a register), and stores the result into R0 (Rd) Adds contents of R1 and number 2 (operand 2 in form of immediate value) and store result in R Moves number 5 (op2, since compiler treats this instruction as MOVLE R0, R0, #5) to R0 (Rd) only if
mediate value or a register with an optional shift
What do these instructions do:
LDR Ra, [Rb] STR Ra, [Rb]
What is the section at the bottom of a piece of as- sembly code called and what does it contain
Value found at [address] found in Rb is loaded into register Ra
Value found in register Ra is stored to [address] found in Rb
A literal pool - a memo- ry area in the same code section to store constants, strings or offsets that oth- ers can reference in a posi- tion-independent manner.
We store memory ad- dresses here in the exam- ple shown in picture
The value found in the reg- ister between these brack-
When we want to load or store something and spec- ify brackets, what does this indicate
ets is a memory address we want to load/store something from/to
In this example, when we debug it, the first line is ldr r0, [pc #12]. Explain this last part
We are loading the value found at the memory ad- dress of PC line 12. This is PC-relative addressing - since we use labels, the compiler calculated the lo- cation of our values spec- ified in the literal pool (PC+12).
You can either use labels or count the exact position of the value in the literal pool. In this case it is 3 hops (4 x 3 = 12) away from the effective PC posi- tion. (Remember, effective PC position, or PC-relative is 2 instructions ahead of current instruction)
STR R2, [R1 #4]!
LDR R3, [R1],
What address mode are What do these instructions do?
What offset form are the current instructions in?
STR R2, [R1, R2] STR R2, [R1, R2]! LDR R3, [R1], R
Pre-indexed (recog- nised by! ): store value found in R2, to the memory address found in R1 plus 4. Base register R1 modified (R1 = R1 + 4)
Post-indexed: load val- ue at memory address found in R1 to R3. Base register modified after: R = R1 + 4 Register used as offset - i.e. used when your code wants to access an array where the index is comput- ed at run-time
Offset: store value found in R2 to memory address found in R1 with the offset R
Pre-indexed (recog- nised by! ): store value
What address mode are What do these instructions do?
What offset form are the current instructions in?
STR R2, [R1, R2, LSL #2]
STR R2, [R1, R2, LSL #2]!
LDR R3, [R1], R2, LSL
What address mode are
found in R2 to memory ad- dress found in in R1 with offset R2. Base register modified: R1 = R1 + R
Post-indexed: load val- ue at memory address found in R1 to register R2, then modify base register: R1 = R1 + R Scaled register at the off- set, LDR Ra, [Rb, Rc, ], Rb is base reg- ister, Rc is immediate off- set left/right shifted - bar- rel shifter scales the offset. Example use when using loops to iterate over an ar- ray,.
Offset: store value found in r2 to the memory ad- dress found in R1 with the offset R2 left-shifted by 2
Pre-indexed (recog-
