12 Lab 12 - Implementation of Synchronous
Counter using Flip Flops
12.1 Objective
To understand the working of a synchronous counter using the flip flops basic knowledge.
12.2 Theory
12.2.1Synchronous Counter
The external clock signal is connected to the clock input of EVERY individual flip-flop within the
counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same time
giving a fixed time relationship. In other words, changes in the output occur in “synchronization”
with the clock signal.
The result of this synchronization is that all the individual output bits changing state at exactly the
same time in response to the common clock signal with no ripple effect and therefore, no
propagation delay.
12.2.2Triggering A Synchronous Counter
Synchronous Counters use edge-triggered flip-flops that change states on either the “positive-edge”
(rising edge) or the “negative-edge” (falling edge) of the clock pulse on the control input resulting in
one single count when the clock input changes state.
Generally, synchronous counters count on the rising-edge which is the low to high transition of the
clock signal and asynchronous ripple counters count on the falling-edge which is the high to low
transition of the clock signal.
It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state, but
this makes it easier to link counters together because the most significant bit (MSB) of one counter
can drive the clock input of the next.
This works because the next bit must change state when the previous bit changes from high to low –
the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-out
and a carry-in pin for linking counters together without introducing any propagation delays.
