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A binary coded decimal (BCD) is a serial digital counter that counts ten digits and it resets for every new clock input.
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A decade counter is one that goes through 10 unique output combinations and then resets as the clock proceeds further. Since it is an MOD-10 counter, it can be constructed with a minimum of four flip- flops. A four-bit counter would have 16 states. By skipping any of the six states by using some kind of feedback or some kind of additional logic, we can convert a normal four-bit binary counter into a decade counter. A decade counter does not necessarily count from 0000 to 1001. It could even count as 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 0011, …. In this count sequence, we have skipped 0000, 0001, 0010, 1101, 1110 and 1111. BCD COUNTER:- A BCD counter is a special case of a decade counter in which the counter counts from 0000 to 1001 and then resets. The output weights of flip-flops in these counters are in accordance with 8421-code. For instance, at the end of the seventh clock pulse, the counter output will be 0111, which is the binary equivalent of decimal 7. In other words, different counter states in this counter are binary equivalents of the decimal numbers 0 to 9. These are different from other decade counters that provide the same count by using some kind of forced feedback to skip six of the natural binary counts.
A binary coded decimal (BCD) is a serial digital counter that counts ten digits and it resets for every new clock input. As it can go through 10 unique combinations of output, it is also called as “Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010, 1011, 1110, 1111, 0000, and 0001 and so on. A 4 bit binary counter will act as decade counter by skipping any six outputs out of the 16 (24) outputs. The output of the NAND gate is connected in parallel to the clear input ‘CLR’ to all the flip flops.
Working:- When the Decade counter is at REST, the count is equal to 0000. This is first stage of the counter cycle. When we connect a clock signal input to the counter circuit, then the circuit will count the binary sequence. The consecutive clock pulses can make the circuit to count up to 9 (1001). The next clock pulse advances to count 10 (1010). Then the ports X 1 and X 3 (MSB) will be high. As we know that for high inputs, the NAND gate output will be low. The NAND gate output is connected to clear input, so it resets all the flip flop stages in decade counter. This means the pulse after count 9 will again start the count from count 0. Decade Counter Truth Table:-
The state transition diagram is a graphical representation of different states of a given sequential circuit and the sequence in which these states occur in response to a clock input. Different states are represented by circles, and the arrows joining them indicate the sequence in which different states occur. As an example, following figure shows the state transition diagram of an MOD- 8 binary counter. Clock count Output bit pattern Decimal X 3 X 2 X 1 X 0 value 1 0 0 0 0 0 2 0 0 0 1 1 3 0 0 1 0 2 4 0 0 1 1 3 5 0 1 0 0 4 6 0 1 0 1 5 7 0 1 1 0 6 8 0 1 1 1 7 9 1 0 0 0 8 10 1 0 0 1 9 11 Counter resets its outputs back to zero