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Features
- Compatible with MCS-51 ®^ Products
- 8K Bytes of In-System Programmable (ISP) Flash Memory - Endurance: 1000 Write/Erase Cycles
- 4.0V to 5.5V Operating Range
- Fully Static Operation: 0 Hz to 33 MHz
- Three-level Program Memory Lock
- 256 x 8-bit Internal RAM
- 32 Programmable I/O Lines
- Three 16-bit Timer/Counters
- Eight Interrupt Sources
- Full Duplex UART Serial Channel
- Low-power Idle and Power-down Modes
- Interrupt Recovery from Power-down Mode
- Watchdog Timer
- Dual Data Pointer
- Power-off Flag
Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus- try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro- grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con- tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
Rev. 1919A-07/
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT89S
2 AT89S
TQFP
1 2 3 4 5 6 7 8 9
10 11
33 32 31 30 29 28 27 26 25 24 23
4443424140393837363534
1213141516171819202122
(MOSI) P1. (MISO) P1. (SCK) P1. RST (RXD) P3. NC (TXD) P3. (INT0) P3. (INT1) P3. (T0) P3. (T1) P3.
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
P1.4P1.3P1.2P1.1 (T2 EX)P1.0 (T2)NCVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)
(WR) P3.6(RD) P3.
XTAL2XTAL1GNDGND (A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.
PLCC
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
(MOSI) P1. (MISO) P1. (SCK) P1. RST (RXD) P3. NC (TXD) P3. (INT0) P3. (INT1) P3. (T0) P3. (T1) P3.
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
(^6543214443424140)
1819202122232425262728
(WR) P3.6(RD) P3.
XTAL2XTAL1GND
NC (A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.
P1.4P1.3P1.2P1.1 (T2 EX)P1.0 (T2)NCVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)
Pin Configurations
PDIP
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
(T2) P1. (T2 EX) P1. P1. P1. P1. (MOSI) P1. (MISO) P1. (SCK) P1. RST (RXD) P3. (TXD) P3. (INT0) P3. (INT1) P3. (T0) P3. (T1) P3. (WR) P3. (RD) P3. XTAL XTAL GND
VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
4 AT89S
Pin Description
VCC
Supply voltage.
GND Ground.
Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs.
Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.
Port 0 also receives the code bytes during Flash program- ming and outputs the code bytes during program verifica- tion. External pullups are required during program verification.
Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL ) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL ) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul- lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL ) because of the pullups. Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only dur- ing a MOVX or MOVC instruction. Otherwise, the pin is
Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) P1.5 MOSI (used for In-System Programming) P1.6 MISO (used for In-System Programming) P1.7 SCK (used for In-System Programming)
Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)
AT89S
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN Program Store Enable (PSEN) is the read strobe to exter- nal program memory.
When the AT89S52 is executing code from external pro- gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V (^) CC for internal program execu- tions. This pin also receives the 12-volt programming enable volt- age (VPP ) during Flash programming. XTAL Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL Output from the inverting oscillator amplifier.
Table 1. AT89S52 SFR Map and Reset Values
0F8H 0FFH
0F0H 00000000 B 0F7H
0E8H 0EFH
0E0H 00000000 ACC 0E7H
0D8H 0DFH
0D0H 00000000 PSW 0D7H
0C8H 00000000 T2CON XXXXXX00T2MOD 00000000 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 0CFH
0C0H 0C7H
0B8H (^) XX000000IP 0BFH
0B0H 11111111 P3 0B7H
0A8H (^) 0X000000IE 0AFH
0A0H 11111111 P2 XXXXXXX0AUXR1 XXXXXXXXWDTRST 0A7H
98H 00000000 SCON XXXXXXXXSBUF 9FH
90H 11111111 P1 97H
88H 00000000 TCON 00000000 TMOD 00000000 TL0 00000000 TL1 00000000 TH0 00000000 TH1 XXX00XX0AUXR 8FH
80H 11111111 P0 00000111 SP 00000000 DP0L 00000000 DP0H 00000000 DP1L 00000000 DP1H 0XXX0000PCON 87H
AT89S
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the
appropriate value before accessing the respective Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.
Table 3a. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00XX0B Not Bit Addressable
- – – WDIDLE DISRTO – – DISALE Bit 7 6 5 4 3 2 1 0
- Reserved for future expansion DISALE Disable/Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Reset out DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only WDIDLE Disable/Enable WDT in IDLE mode WDIDLE 0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode
Table 3b. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B Not Bit Addressable
- – – – – – – DPS Bit 7 6 5 4 3 2 1 0
- Reserved for future expansion DPS Data Pointer Register Select DPS 0 Selects DPTR Registers DP0L, DP0H 1 Selects DPTR Registers DP1L, DP1H
8 AT89S
Memory Organization
MCS-51 devices have a separate address space for Pro- gram and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S52, if EA is connected to V (^) CC , program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.
Data Memory
The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail- able as stack space.
10 AT89S
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles ( oscillator periods) are required to recognize a 1-to-0 transi- tion, the maximum count rate is 1/24 of the oscillator fre- quency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.
Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
Figure 5. Timer in Capture Mode
Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 6. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer regis- ters, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
OSC
T2EX PIN EXF
T2 PIN
TR
EXEN
C/T2 = 0
C/T2 = 1
CONTROL
CAPTURE
OVERFLOW
CONTROL
TRANSITION DETECTOR (^) INTERRUPTTIMER 2
÷
RCAP2H RCAP2L
TH2 TL2 TF
AT89S
Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)
Table 4. T2MOD – Timer 2 Mode Control Register
OSC
EXF
TF
T2EX PIN
T2 PIN
TR
EXEN
C/T2 = 0
C/T2 = 1
CONTR OL
RELO AD
CONTROL
TRANSITION DETECTOR
TIMER 2 INTERRUPT
÷
RCAP2H RCAP2L
TH2 TL
OVERFLOW
T2MOD Address = 0C9H Reset Value = XXXX XX00B Not Bit Addressable
- – – – – – T2OE DCEN Bit 7 6 5 4 3 2 1 0
Symbol Function
- Not implemented, reserved for future T2OE Timer 2 Output Enable bit DCEN When set, this bit allows Timer 2 to be configured as an up/down counter
AT89S
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Fig- ure 8.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation.
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator fre- quency). The baud rate formula is given below.
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 8. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not gener- ate an interrupt. Note too, that if EXEN2 is set, a 1-to- transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
Figure 9. Timer 2 in Clock-Out Mode
Modes 1 and 3 Baud Rates Timer 2 Overflow Rate 16
Modes 1 and 3 Baud Rate
--------------------------------------- Oscillator Frequency 32 x [65536-RCAP2H,RCAP2L)]
OSC
EXF
P1. (T2)
P1. (T2EX)
TR
EXEN
C/T2 BIT
TRANSITION DETECTOR
TIMER 2 INTERRUPT
T2OE (T2MOD.1)
÷2 (^) (8-BITS)TL
RCAP2L RCAP2H
TH (8-BITS)
÷
14 AT89S
Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 9. This pin, besides being a regu- lar I/O pin, has two alternate functions. It can be pro- grammed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator fre- quency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simulta- neously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.
Interrupts
The AT89S52 has a total of six interrupt vectors: two exter- nal interrupts (INT0 and INT1), three timer interrupts (Tim- ers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimple- mented. In the AT89S52, bit position IE.5 is also unimple- mented. User software should not write 1s to these bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Table 5. Interrupt Enable (IE) Register
Figure 10. Interrupt Sources
Clock-Out Frequency Oscillator Frequency 4 x [65536-(RCAP2H,RCAP2L)]
(MSB) (LSB) EA – ET2 ES ET1 EX1 ET0 EX Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt.
Symbol Position Function EA IE.7 Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
- IE.6 Reserved. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. User software should never write 1s to unimplemented bits, because they may be used in future AT89 products.
IE
IE
1
1
0
0
TF
TF
INT
INT
TI RI TF EXF
16 AT89S
Program Memory Lock Bits
The AT89S52 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly.
Programming the Flash – Parallel Mode
The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers.
The AT89S52 code memory array is programmed byte-by- byte.
Programming Algorithm: Before programming the AT89S52, the address, data, and control signals should be set up according to the Flash programming mode table and Figures 13 and 14. To program the AT89S52, take the fol- lowing steps:
- Input the desired memory location on the address lines.
- Input the appropriate data byte on the data lines.
- Activate the correct combination of control signals.
- Raise EA/V (^) PP to 12V.
- Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 50 μs.
Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89S52 features Data Polling to indi- cate the end of a byte write cycle. During a write cycle, an attempted read of the last byte written will result in the com- plement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be verified directly by reading them back. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (100H) = 52H indicates 89S (200H) = 06H Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ALE/PROG low for a dura- tion of 200 ns - 500 ns. In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms. During chip erase, a serial read from any address location will return 00H at the data output.
Programming the Flash – Serial Mode
The Code memory array can be programmed using the serial ISP interface while RST is pulled to V (^) CC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is set high, the Programming Enable instruction needs to be executed first before other opera- tions can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is required. The Chip Erase operation turns the content of every mem- ory location in the Code array into FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The maximum serial clock (SCK)
Table 7. Lock Bit Protection Modes
Program Lock Bits LB1 LB2 LB3 Protection Type 1 U U U No program lock features 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled 3 P P U Same as mode 2, but verify is also disabled 4 P P P Same as mode 3, but external execution is also disabled
AT89S
frequency should be less than 1/16 of the crystal fre- quency. With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz.
Serial Programming Algorithm
To program and verify the AT89S52 in the serial program- ming mode, the following sequence is recommended:
- Power-up sequence:
Apply power between VCC and GND pins. Set RST pin to “H”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pin and wait for at least 10 milliseconds.
- Enable serial programming by sending the Pro- gramming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock sup- plied at pin SCK/P1.7 needs to be less than the CPU clock at XTAL1 divided by 16.
- The Code array is programmed one byte at a time by supplying the address and data together with the
appropriate Write instruction. The write cycle is self- timed and typically takes less than 1 ms at 5V.
- Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/P1.6.
- At the end of a programming session, RST can be set low to commence normal device operation. Power-off sequence (if needed): Set XTAL1 to “L” (if a crystal is not used). Set RST to “L”. Turn V (^) CC power off. Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during a write cycle an attempted read of the last byte written will result in the com- plement of the MSB of the serial output byte on MISO.
Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in Table 10.
AT89S
Figure 15. Flash Programming and Verification Waveforms – Parallel Mode
Flash Programming and Verification Characteristics (Parallel Mode)
T (^) A = 20°C to 30°C, VCC = 4.5 to 5.5V
Symbol Parameter Min Max Units VPP Programming Supply Voltage 11.5 12.5 V I (^) PP Programming Supply Current 10 mA I (^) CC VCC Supply Current 30 mA 1/t (^) CLCL Oscillator Frequency 3 33 MHz t (^) AVGL Address Setup to PROG Low 48t (^) CLCL t (^) GHAX Address Hold After PROG 48t (^) CLCL t (^) DVGL Data Setup to PROG Low 48t (^) CLCL t (^) GHDX Data Hold After PROG 48t (^) CLCL t (^) EHSH P2.7 (ENABLE) High to V (^) PP 48t (^) CLCL t (^) SHGL VPP Setup to PROG Low 10 μs t (^) GHSL VPP Hold After PROG 10 μs t (^) GLGH PROG Width 0.2 1 μs t (^) AVQV Address to Data Valid 48t (^) CLCL t (^) ELQV ENABLE Low to Data Valid 48t (^) CLCL t (^) EHQZ Data Float After ENABLE 0 48t (^) CLCL t (^) GHBL PROG High to BUSY Low 1.0 μs t (^) WC Byte Write Cycle Time 50 μs
t (^) GLGH t (^) GHSL
t (^) AVGL
t (^) SHGL
t (^) DVGL t (^) GHAX
t (^) AVQV
t (^) GHDX
t (^) EHSH t (^) ELQV
t (^) WC
BUSY (^) READY
t (^) GHBL
t (^) EHQZ
P1.0 - P1. P2.0 - P2. P3.
ALE/PROG
PORT 0
LOGIC 1 EA/V (^) PP LOGIC 0
VPP
P2. (ENABLE)
P3. (RDY/BSY)
PROGRAMMING ADDRESS
VERIFICATION ADDRESS
DATA IN DATA OUT
20 AT89S
Figure 16. Flash Memory Serial Downloading
Flash Programming and Verification Waveforms – Serial Mode
Figure 17. Serial Programming Waveforms
P1.7/SCK
DATA OUTPUT
INSTRUCTION INPUT
CLOCK IN
3-33 MHz
P1.5/MOSI
VIH
XTAL
XTAL1 RST GND
VCC
AT89S
P1.6/MISO
VCC
7 6 5 4 3 2 1 0
