Basics of State Machine Design - Digital System Design - Lecture Slides, Slides of Digital Systems Design

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Basics of State Machine Design

Finite-State Machines (FSMs)

• Want sequential circuit with

particular behavior over time

• Example: Laser timer

– Push button: x=1 for 3 clock

cycles

– How? Let’s try three flip-flops

• b=1 gets stored in first D flip-flop
• Then 2nd flip-flop on next cycle,

then 3rd flip-flop on next

• OR the three flip-flop outputs, so x

should be 1 for three cycles

Controller x

b

clk

laser

patient

D Q D Q D Q

clk

b

x

Describing the Behavior of a

Sequential Circuit: FSM

• Finite-State Machine (FSM)
  • A way to describe desired behavior of sequential circuit - Akin to Boolean equations for

combinational behavior

• List states, and transitions among states - Example: Make x change

toggle (0 to 1, or 1 to 0) every

clock cycle

• Two states: “Off” (x=0), and

“On” (x=1)

• Transition from Off to On, or

On to Off, on rising clock edge

• Arrow with no starting state

points to initial state (when

circuit first starts)

4

Outputs: x

Off On

x=0 x=

clk^

clk^

FSM Example: 0,1,1,1,repeat

• Want 0, 1, 1, 1, 0, 1, 1,

– Each value for one

clock cycle

• Can describe as FSM

– Four states

– Transition on rising

clock edge to next state

5

Off On1On2 On3 Off On1On2On3Off

clk

x

State

Outputs:

Outputs: x

Off On1 On2 On

clk^

clk^

x=0 clk^ x=1 x=1^ clk^ x=

FSM Simplification: Rising Clock Edges Implicit

• Showing rising clock on every

transition: cluttered

• Make implicit -- assume every edge has rising clock, even if not shown
• What if we wanted a transition without a rising edge - We don’t consider such

asynchronous FSMs -- less

common, and advanced topic

• Only consider synchronous FSMs

-- rising edge on every transition

7

Note: Transition with no associated condition thus transistions to next state on next clock cycle

On1 On2 On

Off

x=1 x=1 x=

x=

b’

b

Inputs: b; Outputs: x

On1 On2 On

Off

x=1 x=1 x=

x=

b’

clk^

clk^

clk^ ^

*clk^

b *clk ^

Inputs: b; Outputs: x

FSM Definition

 FSM consists of

 Set of states

 Ex: {Off, On1, On2, On3}

 Set of inputs, set of outputs

 Ex: Inputs: {b}, Outputs: {x}

 Initial state

 Ex: “Off”

 Set of transitions

 Describes next states  Ex: Has 5 transitions

 Set of actions

 Sets outputs while in states  Ex: x=0, x=1, x=1, and x=

8

Inputs: b; Outputs: x

On1 On2 On

Off

x=1 x=1 x=

x=

b’

b

We often draw FSM graphically,

known as state diagram

Can also use table (state table), or textual languages

FSM Example: Secure Car Key (cont.)

• Nice feature of FSM
  • Can evaluate output

behavior for different

input sequence

• Timing diagrams show

states and output

values for different

input waveforms

10

K1 K2 K3 K r=1 r=1 r=0 r=

Wait r=

Inputs: a; Outputs: r

a^ a’

Wait Wait K1 K2 K3 K4 Wait Wait

clk Inputs

Outputs

St at e

a

r

clk Inputs a

Wait Wait K1 K2 K3 K4 Wait^ K

Output

State

r

Q: Determine states and r value for given input waveform:

FSM Example: Code Detector

• Unlock door (u=1) only when

buttons pressed in sequence:

• start, then red, blue, green, red
• Input from each button: s, r, g, b
• Also, output a indicates that some colored button is being pressed
• FSM
• Wait for start (s=1) in “Wait”
• Once started (“Start”)
• If see red, go to “Red1”
• Then, if see blue, go to “Blue”
• Then, if see green, go to “Green”
• Then, if see red, go to “Red2”
• In that state, open the door (u=1)
• Wrong button at any step, return to “Wait”, without opening door

11

Start

Red Green Blue

s

r g b a

Door lock

u Code detector

Q: Can you trick this FSM to open the door, without knowing the code? A: Yes, hold all buttons simultaneously

Wait

Start

Red1 Blue Green Red

s’

a’

ar’ ab’ ag’ ar’

a’

ab ag^ ar a’ a’ u=

u=0 (^) ar

u=0 (^) s

u=0 u=0 (^) u=

Inputs: s,r,g,b,a; Outputs: u

Common Pitfalls Regarding Transition

Properties

• Only one condition

should be true

• For all transitions

leaving a state

• Else, which one?
• One condition must be

true

• For all transitions

leaving a state 13

a

b

ab=11 –

next state?

a

a’b

Verifying Correct Transition

Properties

 Can verify using Boolean algebra

 Only one condition true: AND of each condition pair (for transitions leaving a state)

should equal 0  proves pair can never simultaneously be true

 One condition true: OR of all conditions of transitions leaving a state) should equal 1  proves at least one condition must be true

 Example

14

a

a’b

a + a’b = a*(1+b) + a’b = a + ab + a’b = a + (a+a’)b = a + b Fails! Might not be 1 (i.e., a=0, b=0)

Q: For shown transitions, prove whether:

* Only one condition true (AND of each pair is always 0)

* One condition true (OR of all transitions is always 1)

a * a’b = (a * a’) * b = 0 * b = 0 OK!

Answer:

Design Process using FSMs

1. Determine what needs to be remembered

 What will be stored in memory?

2. Encode the inputs and outputs in binary (if

necessary)

3. Construct a state diagram of the behavior of

the desired device

 Optionally – minimize the number of states

needed

4. Assign each state a binary number (code)

Example Design 1

• Design a circuit that has input w and output

z

– All changes are on the positive edge of the clock

– The output z = 1 only if w = 1 for both of the

two preceding clock cycles

• Note: z does not depend on the current w

• Sample timing:

cycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10

w: 0 1 0 1 1 0 1 1 1 0 1 z: 0 0 0 0 0 1 0 0 1 1 0

• Corresponding state diagram

 - Step - C z = 

• w = 0 A z = 0 B z = - w = - w = - w =
  • w = 0 w =

Step 4

 Assign binary numbers to states

 Since there are 3 states, we need 2 bits

 2 bits  2 flip-flops

 Many assignments are possible

 One obvious one is to use:

 A: 00 (or 10 instead)

 B: 01

 C: 11

 This choice may not be “optimal”

 State assignment is a complex topic all to itself!