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Build Inverter in Schematic View
In this tutorial, you will start using Cadence and design your first CMOS gate: an inverter. Believe or not, working on the first inverter is the most important part of the overall laboratory work. You will learn much. Do not pass the steps unless you have understood what you are doing. Do not forget that, you have to learn every step in this tutorial.
� Starting Library Manager
Before starting to your first design, you need to create a library, which will contain all the circuits that you will implement during this laboratory.
� Create New Library
In Library Manager window, click on File->New ->Library.... You will see the following window. Enter the name of library (example shown: ELE462) where you expect to store your own designed cells. Attach this library to an existing technology (example shown: AMI 0.60 micron technology) so that the Cadence tools would know the technology specifics of your design (like SPICE models, DRC rules, ERC rules, etc.)
You can also use "compile tech library". This creates a local copy of the technology library in your run directory, thus it is not very efficient in the sense that every use has a copy of an indentical library. It is also not very flexible in the sense if there is any change made to this technology library, each user has to update his copy of the compiled tech library. Because of these two reasons, we prefer "attach to existing tech libary" to "compile tech library".
Not only you have created a library "ELE462" of your own, but you have also included its associated technology library "NCSU_TechLib_ami06" in your library path.
� Create a new schematic
In your Library Manager window, click on the File->New->Cellview. A pop-up dialogue box appears. Click on the library name button and select "ELE462". Click on the Tool button to select "Composer-Schematic". The View Name will automatically change to "schematic". Enter the name of the cell you wish to design in Cell Name. For the tutorial case, we design an inverter.
device. To place the instance, activate the schematic window and click the left mouse button to put the instance at the place desired.
Note in Cadence schematic composers and layout editors, a command will not terminate unless the user cancels it or the user starts a new command. In this case, you can see another instance is ready to be placed right after you placed the first instance. To terminate the current operation (which is "add instance" in this case), press ESC key on the keyboard. In fact, you can always cancel the current operation in schematic or layout editors by pressing ESC key.
� Set Properties
To set the property of the instance that you just placed or any object in your schematic or layout design, select the object by clicking on it and then go to "Edit->properties->Object..." (or by typing q). An object properties editing form will pop up.
Change the width or length of the gate to the desired value. In this case, we use the default value. Following the same techniques, we can add an instance of PMOS transistor.
� Connect the instances with wires
To connect the PMOS and NMOS devices or any electrically connected devices, click on Add->Wire(narrow) in the schematic window (or type w). Click at the terminal where the wire starts and click at the terminal where the wire ends, a wire will be automatically added. If you are not satisfied with the automatic
� Check and save the designs
After the design has been completed, click on "Design->Check and Save" to check and save your designs. Check the CIW window to see if there is any errors in your designs. The following image shows the completed design of inverter.
� Hot keys
i: Add instances q: Edit properties w: Add wires p: Add a pin l: Label a wire z: Zoom in Z: Zoom out by 2X f: fit the schematic in your schematic window right mouse button: repeat last command
If you don't like this rectangular symbol that is automatically created by the tool, you can create a symbol of you own.
� Create a symbol from scratch
As long as we know the inputs and outputs of a cell, we can create a symbol for it. We can either draw the lines and arcs ourselves (which is pretty self-explanary and the hot keys are very much similar to the schematic composer window), or we can borrow some existing drawings and modify them. Click on Add->Import Symbol... and the following dialogue box appears.
Click on Browse to find a symbol in other libraries. In our case, we borrowed the symbol from cell inv of library NCSU_Digital_Parts. Since these two designs are essentially the same, they have exactly the same number of input/output pins. We
only have to modify the input and output pin names so that they conform to the pin names in our schematic design. The final symbol is shown below.
In the schematic design window, click on Tools-> Simulation->Spectre to start the Spectre. Unlike many other tools, there is no pop up window. Instead, You will see an added item "spectre" on the menu of the schematic window.
� Simulation in Analog Environment
Now, click on "Tools->Analog Environment" in order to run analog simulator. Click on "Setup->Set Modles Path", delete the current directory and add new directory /opt/cadence/local/models/spectre/nom as the model directory.
Click on Analyses->Choose. "tran" is chosen as the default analysis time. Write any number of periods as you like. Click OK.
Now, it is time to determine the nodes that will be observed. Click on \texttt{
Outputs->To Be Plotted->Select on Schematics}. This will let you choose the nodes to be observed. Focus the schematics editor and click on the wires at the input and output of the inverter.
There are 2 types of signals to be observed after the simulation: voltage and current. If you click on wire, you select that wire's voltage as the observed signal. If you click on the node like the input of the inverter, you select the current of that node as the observed signal. You see a circle on that node. You will work on voltage here.
Once this is done, go to Simulation on the Analog Environment Window and select Netlist and Run. Wait for a few seconds and after the simulation is finished, a waveform window will automatically appear.
Create Custom Layouts
By now, we have already created the schematic and have simulated our design with verilog-XL and spectre. The next step in the design process is to create the layout for the circuit. A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is the most critical step in the design process because it determines whether your design is finally going to be work or not.
Before we get into the layout, first we need to choose the design process we are going to use for the layout. This has in fact been specified when we attach our designs to a specific process when we create the library. In our project, the design process we are going to use is the AMI C5N process.
Now we give a tutorial on Virtuoso through creating an example layout for the inverter cell.
� Create a layout cellview
In the library manager window, click on the File -> New -> CellView. Choose tools as Virtuoso.
Two windows appear. One is the LSW window that contains the layer information and the other is the layout editor.
In order to show the pin names, select Pin Names in Display Controls. You can also change the Grid Controls to alter the Minor Spacing and Major Spacing. But do not change the X Snap Spacing or Y Snap Spacing and leave them to be half lambda. Finally you can save your changes to the .cdsenv file.
� Draw layout shapes
Before we start to draw the layout, we should understand that each shape in a layout is associated with a layer. Basic layers in AMI C5N process include Nwell; active; N-select; P-select; poly; metal1,2,3; contact; via1,2; glass; pad. We will not use P-well in the AMI C5N process. There are a few layers that are used just to help layout, but does not correspond to any physical layer. For example, text layer is used to annotate the design. Cap_id, res_id and dio_id are used for layout extraction. If we want to draw a shape of a certain layer, we should click on that layer in the LSW before we draw any shape.
There are two basic types of shapes we can draw, path and polygon. Path is often used to represent "wires". Thus we often use paths to draw metal 1, 2, 3 and poly. This is not a restriction, but rather a common pratice. In fact, you can use path for any layer and you can also use polygon for any layer. To specify a path, click on Create -> Path in the layout window and the following windows appears.
In this window, we can specify the width for the path we draw. The default value in the width is the minimum width of the layer (metal1 in this case). We can also specify the draw style like "justification" and "end type" etc. Now we can activate the layout window and click at the point where you want the wire to start and click at every point where you want to change the direction of the wire till finally you end of the wire by double clicking at the endpoint.
The other type of the shape is polygon. Polygons are generally used to represent the "non-wire" layers that In the layout window, click on Create -> Rectangle. The following window appears.
Now in the layout window, click on the two diagonal corners of the rectangle, we can create a rectangle.
� Create an inverter
The AMI C5N process is an Nwell process, thus the substrate is p-substrate. The P-transistor should be created inside the Nwell and the N-transistor should be created outside the N-well on P-substrate directly. We will create an inverter as shown below with the following steps.
the following create pin window appears.
In this window, fill in Terminal Names with inv_out and select Display Pin Name and change I/O Type to be Input. To display the pin nicely, click on Display Pin Name Option and change the height to be 0.5 micron in the "Pin Name Display"
window. Create the pin now by drawing a rectangle over the via and then place the pin name.
- Label the VDD! and GND!pins. Since the power and ground rails all use metal1, we first select the Metal1 pin inside LSW. Follow the steps in 9 except this time the I/O Type is jumper.
� Check and save your design
Before saving the design, we hope to make sure that the design has comform to the design rules. As careful as one might be, it is very hard for a designer to avoid all the design rule errors. To perform the design rule checking, click on Verify -> DRC... in the layout window. A pop up dialogue box will appear.
For a small circuit like an inverter, it is OK just to run the DRC in the flat mode since the running time is short. For a big layout, however, it is wise to run the DRC in a hierarchical mode. In general, hierarchical mode is faster than flat mode, especially for a large layout composed of iterative structures. However, hierarchical DRC might not be accurate in some rare cases. Thus it is a good practice to check a big circuit with hierarchical DRC first and then run a flat DRC
