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CHAPTER 9. DIODES and DIODE CIRCUITS
9.1 INTRODUCTION TO SEMICONDUCTOR ELECTRONICS
The earliest form of non-linear electronics was not based on semiconductor electronics but on devices in which the flow of electrons was contained within a vacuum envelope, or tube. Vacuum tubes were intricate and interesting, but were bulky, hard to make, and easily broken. And their cathode filaments had a limited lifetime. If we should wish to work in outer space where a vacuum is readily available they might make a resurgence. But here on the earth, with its oxygen-nitrogen atmosphere and the discovery that most electronics could be accomplished using semiconductors, vacuum tubes became an obsolescent artifact in the history of electronics.
Semiconductors are interesting and unique in that they may be alloyed to provide an excess of charge carrier densities according to ‘doping’ levels of alloyed impurities. Furthermore the impurity alloying can be patterned using masks, particularly when the impurities can be injected and laid down by means of ion guns and molecular beams and other such weaponry. In addition to these aspects, impurity alloying invites the context of two types of charge-carriers, (1) electrons and (2) holes (what??). Excess electron densities afforded by ‘donor’ impurities speak for themselves. The nomenclature that we identify as ‘holes’ is peculiar to the fact that we are using a solid-state lattice as a medium which will accommodate the absence of an electron at the atomic sites defining the lattice. The absence of an electron represents a positive charge site that may be traded around with much of the same mobility as that of a conduction electron except with an electronic charge measure of +q instead of a –q measure.
The secret, of course, is that semiconductors are a material that is neither metal nor insulator. They are characterized by a band-gap between (1) the valence energies that bind the crystal together and (2) the higher energies in which electrons are not bound but are (reasonably) free to roam throughout the material. The physics is entertaining, as most physics usually is. The band-gap context is shown by figure 9.1-1. If the band-gap is overly large (e.g. E (^) G > 5 ev) the material is then an insulator.
Figure 9.1-1. Band-gap context of semiconductors.
Notice that the higher-energy band is labeled as the ‘conduction’ band with lower band edge EC , since electrons at these energies are not strongly bound and can therefore be pushed around by the slightest of E-fields, much like the electrons within a metal. The context is even more emphatic when viewed as a lattice, such as that of Silicon, which is tetravalent, and therefore is bound (covalently) to four nearest neighbors as shown by figure 9.1-2.
(a) Donor impurities under E-field (b) Acceptor impurities under E-field (movement of loose electrons) (movement of loose holes)
Figure 9.1-2. The Si lattice in 2-dimensions, showing covalent (shared) electrons between atomic lattice nodes. (Actually the lattice is more like that of figure 9.1-4 (a) for which four nearest neighbors are at tetrahedral vertices.)
The two-dimensional representation is most informative since we can look upon the semiconductor in terms of the effect of appropriate impurities. For example, as shown by the figure, if a phosphorus (pentavalent) impurity is introduced into the lattice, its extra valence electron becomes a step-child. It is therefore prone to depart and wander around the neighborhood. On the other hand if a boron (trivalent) impurity is introduced within the lattice it leaves a ‘hole’ (hence the name). And the hole will skip from one site to the next as neighboring covalent electrons fall into it and leave an absence (hole) at their former home site. Once again the physics is fun, particularly when the lattice structure is introduced, for which the simple band-gap context takes on a periodic geometric context.
But the context is still relatively simple. A hole is very much like the little bubblets that you will see when you drop by your local tavern for a tall cold ginger ale. Notice that bubblets fall upward, whereas pellets fall downward. In the context of semiconductors the gravitational field would be replaced by an electric field for which ‘holes’ are equivalent to bubblets and the electrons are equivalent to pellets.
It is appropriate that the nomenclature reflect the types of charge carriers that are induced by the impurity alloying. And so those materials that have impurity doping which contributes electrons (also called donor impurities) are identified as ‘n-type’ (i.e. suffused with negative charge carriers). Those materials which accept electrons (and leave holes) (and are also called acceptor impurities) are identified as ‘p-type’ (i.e. suffused with positive charge carriers).
And thus we can pattern the semiconductors in terms of their electrical properties as reflected by the type of charge carriers. It only takes a minute level of impurities (usually on the order of 1:10 6 ) to define the character of the semiconductor. Almost everything associated with semiconductor electronics is identified in terms of the incidence and presence of pn junctions.
9.2 PN JUNCTIONS
The metallurgical context of the pn junction is straightforward, although there are all kinds of pn junctions. Semiconductor junctions have variations according to impurity profiles, geometrical options, types of impurities and type of semiconductor. There are probably as many different types of pn junctions as there are different taxonomies of insects. There are even types of junction that aren’t pn junctions but have a lot of the properties thereto. But no matter how clever the construct may be, the simplest pn junction is good with the physics. The nominal manufacturing context is shown by figure 9.2-1. The rest of the story is shown by figure 9.2-2, which is a slice across figure 9.2-1. The electrical properties (characteristics) are the primary subject of interest to the electrical engineer.
Figure 9.2-1. Ion implantation process for pn junction
Notice that figure 9.2-1 also introduces the concept of counter-doping, in which case it is the excess of impurities that define the type of semiconductor. With counter-doping the lower density impurities sites are filled by the opposite type carrier and no longer contribute to the conduction. So the type ( n or p ) is an indication of the majority carriers.
In the vicinity of the junction thermal diffusion will cause electrons to migrate across the boundary from the n-side into hole territory. In doing so the migration leaves behind a layer of uncovered donor sites which become an ionized layer of (+) charges. On the p-side the immigrant electrons fill acceptor sites to the layer depth on the order of microns, creating an ionized layer of the (-) type charge. Consequently the two uncovered layers in the vicinity of the junction boundary induce a formidable built-in electric
field that blocks any further migration of charge across the junction boundary. The built-in field context is a signature of the junction and is represented by figure 9.2-2.
Figure 9.2-2. Uncovered impurity sites in the vicinity of the pn junction boundary
This behavior reveals another context of semiconductors, namely that they accommodate the presence of an electric field, much like an insulator. In the vicinity of a pn junction the thermal statistics induces an E-field strong enough to crackle were it outside the material. And yet the semiconductor material away from the junction contains sufficient mobile charge carrier densities for good conduction.
Since the two opposite polarity uncovered layers (also designated as the space-charge layer) thickness is on the order of microns the junction E-field is huge. Consider the following example:
EXAMPLE 9.2-1: An abrupt junction has a density of (acceptor)( p -type) impurities of NA = 10 16 #/cm^3 and a density of (donor)(= n -type) impurities of ND = 10 15 #/cm^3. (This is called a one-sided junction and
is reflected by the illustration). The field develops a voltage difference due to the band-gap of = 0.8V
which uncovers the doping sites to a layer thickness of 0.18m on the p -side and 1.8m on the n -side. (Notice that this gives charge equilibrium). What is the magnitude of the electric field in V/cm?
Figure E9.2-1: Example slice across an abrupt (idealized) pn junction. Note that charge equilibrium requires that the more lightly-doped uncovered charge layer be much thicker than that for the more
heavily doped side. The donor impurities have density ND = 0.1 × NA and so Wn = 10 × Wp.
SOLUTION: The average separation of charge = 0.5 × ( Wp + Wn ) = 0.5 × (0.18 + 1.8)m = 1.0m.
The E-field is then = (0.8V/1.0m) = 0.8 V/m = 0.8 × 104 V/cm. = 8.0 kV/cm
VT (at T = 25 oC) = .0254 V . 025 V (9.2-3)
The thermal voltage is given an equation number all of its own because the value VT = .025V is employed for most back-of-the-envelope calculations.
The parameter n is called the emission coefficient and is the principal reason why the ideal diode equation is not linear for the entire region of I ( V > 0). In the vicinity of the most likely region of operation 0.7V < V < 0.9V , emission coefficient n approximately = 1. For lower voltages n = 2 (approximately). For voltages higher than 1.2V the resistance of the semiconductor material begins to dominate and the I(V) is linear rather than exponential (which shows up as a roll-off on the logarithmic scale). It should be apparent that the circuit simulator is using more comprehensive mathematical models than just equation (9.2-1) to provide the best possible representation of the diode. So the ideal diode equation is only the first-order part of the story.
The electrical behavior of the junction when it is employed as a circuit component suggests the symbol shown by figure 9.2-3(b). It looks like an arrowhead that points in the direction of forward (also called the ‘easy’) current flow, consistent with figure 9.2-2.
Figure 9.2-3. Physical context and circuit symbol for pn junction (diode).
To be fair, minority-carrier current does flow in the reverse-bias direction. It even increases a tad as the reverse bias is increased (as must always be true). It is important to note that reverse-bias current is on the order of IS = 10 -15^ A = 1.0 fA, depending on the area of the junction. This level of current is less than that for many insulators of like area and tells us that the reverse-biased junction is effectively a very good
insulator. For the 1n914 diode IS = 16.8 × 10 -20^ A, which is about two orders of magnitude smaller than
the conductance of the air in the vicinity of the diode.
The symbolic context also identifies that the junction in reverse-bias is a capacitance, inasmuch as there is a separation of charge and virtually no leakage current. But the junction is also more than a simple plate capacitance because a greater reverse-bias increases the built-in field and uncovers more charge. Hence the layer thicknesses Wn and Wp increase proportionally and therefore the capacitance decreases with the application of more voltage.
Consequently the capacitance of a junction in reverse-bias is voltage dependent. For the (ideal) abrupt junction the behavior is approximately
CJ CJ 0 1 VR J MJ (9.2-4)
This is a Big deal because a voltage-variable capacitance then will have a time constant that can be controlled electronically and then can readjust circuit tuning by use of feedback.
It should also be noted that once the charge carriers are injected across the junction boundary and flow into the opposite type of semiconductor territory they will recombine with their opposite number at a rate
determined by a recombination time constant R. Unfortunately the recombination time constants are
usually not as fast as the higher speeds at which we desire to switch the diode on and off, and the lag gives a commutation effect that limits the ON/OFF time response of the device.
9.3 DIODE CONDUCTANCE MODELS FOR CIRCUIT ANALYSIS
The diode is so named because its vacuum tube forebear had two electrodes. The pn junction is the two- terminal semiconductor equal and it may exist as either a discrete device or as an included part of another device within a fabricated integrated circuit.
Using Newton-Rhapson iterative techniques, circuit simulation software can accomplish the mathematics of section 9.2 very handily. But the non-linear equations that define the physics are not tractable to the quick analysis necessary for making design decisions. Their use by an engineer is worthwhile only for defining circuit software processes and their use otherwise would be mostly a disciplinary exercise. Less- accurate piece-wise linear models are completely adequate for design assessment of circuits containing diodes and the models of choice are indicated by figures 9.3-1(b) and (c).
Figure 9.3-1. Circuit analysis conductance models of the diode. (A ‘1 mA diode’ is represented)
The first one (a) is the ideal diode equation and is only shown for the context of ‘ON’ and ‘OFF’ conduction modes. The second one (b) assumes that once a threshold level V = V is reached, the diode is ‘ON’, the forward conductance (slope) is infinity, and the forward current can be anything > 0. The last
Although the example was simple and direct it also suggests that the voltage loop and DC voltage source are an aside to the rest of the circuit and may be treated as ideal batteries with short-circuit current able to forge a wrench or melt down a battleship if so desired.
As a simplification the voltage sources will be replaced voltage supply ‘rails’, much like we might see if we laid the circuit components down on a printed circuit board or within an integrated circuit. And that brings us to another example, just like that of example 9.3-1, except different.
EXAMPLE 9.3-2: Diodes between voltage rails and analysis by inspection. Find I 2 and V 2.
By inspection
I 2 = 0.1mA V 2 = 4.0V
(or otherwise if not, then)
10 40
I = 0.1 mA
V 2 0 10 0. 24 0. 7 = 4.0 V
Figure E9.3-2. Diode string and analysis by inspection
The solution context ‘by inspection’ should not be unfamiliar and truly is the only practical way to do most aspects of circuit analysis. The CVD and the ideal rectifier model permit us to cut to the chase ‘by inspection’ and acquire values of the electrical facts without cluttering up the analysis with arithmetic.
But also consider that we are dealing with junction diodes that clearly have two ‘states’ (ON and OFF). The previous examples made the visual assumption that the diodes were ‘ON’ and that guided the process. The‘OFF’ state was not considered. But if you were blind you would have to do so, or identify a bias criterion for the ON/OFF state of the diode component.
The bias assessment is therefore a part of the inspection analysis just as much if not more than the rough mathematical analysis. Consider the following example
EXAMPLE 9.3-3: A diode string between voltage dividers. Find V 1 , V 2 and ID.
Figure E9.3-3. Diode string and resistance network.
SOLUTION: If you look at the voltage dividers to each side of the diode string it should be evident that V 1 is greater than V 2 by inspection since the naked voltage dividers would give V 1 = 6.67V and V 2 = 2.0V. You do not need the naked values for V 1 and V 2 to affirm that the diode string has no choice but to be conducting. You could even hazard a WAG (wild-eyed guess) as to what voltage values would result since V 1 will be pulled down by the diode current and V 2 will be pulled up. In the analysis of electronic circuits with non-linear elements, even a WAG may be adequate, - even on a quiz, if within 10%.
Turning to mathematics and nodal analysis at V 1 and V 2 , respectively, we get
V 1 : V 1 (^) 0. 5 0. 25 0. 5 10 ID 0 and V 1 = V 2 + 2 × 0. V 2 : (^) V 2 0. 25 1. 0 0. 25 10 ID 0
V 2 0. 75 1. 25 1. 4 0. 75 0. 5 0. 25 10 0
So that ^
0
5 1. 05 2
V ^ =^ 3.23 V^ V 1 = 3.23 + 1.4 =^ 4.62 V
And from the V 2 node equation: I (^) D V 2 0. 25 1. 0 0. 25 10 = 1.53mA
The network mathematics invited the use of nodal analysis. Nodal analysis gives node voltages. Circuit simulation software accomplishes its assessment by a modified nodal analysis. But even the circuit simulation software has to make a perceptive preliminary assessment of the node voltages before undertaking its iterative numerical analysis.
Diode characteristics and that of their semiconductor cousins are defined by voltage biases. So options on the voltage states are an essential part of the assessment. The rest of the story is associated with effect of
And the current through D1 is 4.3mA – 1.25mA ID1 = 3.0mA
*And this confirms that diode D1 is conducting, (for which. ID1 > 0) just like we presupposed.
Also note that we can only determine the current through a diode indirectly. So we determine currents through the associated paths and then make use of the law of currents (otherwise known as KCL) to acquire the essential electrical facts for each of the diodes in the circuit. Sometimes the electrical facts are simple, i.e. that the current through the diode = 0 because the diode is in reverse bias.
Emphasis needs to be made that the art of inspection is vital to analysis of circuits that include diodes. More diodes require more inspection. Inspection identifies the allowed and disallowed diode states. Consider the example of a string of diodes as represented by example 9.3-4:
EXAMPLE 9.3-5: Determine node voltages V 1 , V 2. V 3 , V 4 and the currents through each of the diodes for R 1 = 4.0, R 2 = 2.5, R 3 = 2.5 and R 4 = 5.0 (all in k). Assume the CVD model.
Figure E9.3-5: Diode string
SOLUTION: Notice that we have included a ‘state table’ for all of the possible diode states. But just like the previous example it may be assured that some diodes have no choice. For example diode D 1 must always be ON since the current through R 1 has to go somewhere and the diode is correctly oriented for it to do so.
The rest of the possible options are shown by the completed state table. Note that D 3 must also always be on (why?).
Only one of these states is valid. So we pick one and try it out. The rule is (always) ‘simplest first’. And the [ 1 1 1 1 ] state is the most likely candidate since it allows all node voltages be identified by stepping from right to left, beginning with D 4 :
i.e. V 4 = 0.7V, V 3 = 1.4V, V 2 = 0.7V, V 1 = 1.4V
from which we obtain (by inspection) I 1 = 1.25mA, I 2 = 2.0mA, I 3 = 2.0mA and I 4 = 1.0mA.
and for which (1) ID1 = I 1 = 1.25mA (2) ID2 = I 2 – ID1 = 0.75mA (3) ID3 = I 3 – ID2 = 1.25mA And (4) ID4 = ID3 – I 4 = 0.25mA
Since all of these are positive then the assumption that all diode are in a conducting state is true and hence
V 4 = 0.7V , V 3 = 1.4V , V 2 = 0.7V , V 1 = 1.4V
ID1 = 1.25mA , ID2 = 0.75mA , ID3 = 1.25mA , ID4 = 0.25mA
Notice that we do not highlight the answers until they are confirmed.
Because diodes have two state (ON, OFF) their analysis becomes a binary set of possible states. In this case it should be clear that some states cannot possibly exist and there is no point in pursuing them. And once again the process of analyzing diode circuits needs to use inspection to identify what states can exist and are worth a pursuit.
Note that the engineer (or his software) has to undertake this sorting process and identify the possible allowed diode states before invoking any mathematics. Otherwise he/she is just spitting into the wind.
The rest of the story is that there were still a handful of possible states left. Be assured that only one state can be true, and so the ‘art’ of electronics is to choose wisely. But have no cause to fear. The art is straightforward and always follows the rule: ‘Try the simplest one first’
Even so, we have to realize that the simplest possibility may not be the ‘lucky’ correct one, as was the case for this example.
In fact were resistance R 4 = 2.5kin exercise 9.3-5, then the value of ID4 = - 0.75mA, which is impossible. And so in that case the simplest state would not be valid. Therefore it would be necessary to test the next simplest case, whichever one that might be.
In exercise 9.3-5 the next simplest state would probably be the one for which (D 1 ,D 2 ,D 3 ,D 4 ) = [1 0 1 0] since it is merely two separated diode strings.
Figure 9.4-2(a). Diode bridge and load, also called a full-wave rectifier (FWR). Figure 9.4-2(b). Voltage across the load due to current through the diodes for the FWR (a.k.a. FWB).
Note that the contribution to IL comes from both polarities (1) the conductive loop through D1 and D formed when Vs > 0 and (2) the conductive loop through D3 and D4 when Vs < 0. The outcome is shown by Figure 9.4-2(b)
The FWR topology may also be drawn in bridge form shown by figure 9.4-5.
Figure 9.4-3 Full-wave rectifier (FWR) topology of figure 9.4-2(a) drawn as a full-wave bridge (FWB). Compare the position of the diodes between this figure and that of figure 9.4-2(a)
And the same mathematics applies to the FWR as equation (9.4-1) except there are two half waves that add up to give a factor of two
VL t VL
for which the average power delivered to the load is
L
L L R
V
P t
2 2
( )^4
L
L R
0. 4 V^^2 (9.4-4)
Average current through RL identifies one-one with the count of rectified half-waves. So if the source is three-phase (3) then the count of half-waves across RL is three and the current is of the form represented by figure 9.4-4.
Figure 9.4-4. Three-phase sum of rectified currents. The outcome shows up as a steady-state signal with
a ripple of peak-peak amplitude VR and frequency = 6 × f 0.
The averaged output level for the 3 rectifier is then
VL^ t^ VL
and the power to the load is
L
L L R
P t V^2 2 ( ) ^9 (^) L
L R
0. 91 V^^2 (9.4-6)
The output voltage level VL , as well as being close to unity, is also one for which the ripple is small and mathematically of the value
V (^) L 0. 134 V L =^ VR (9.4-7)
Equations (9.4-5) through (9.4-7) point out an aspect of the AC-DC converter that is of importance, namely an output that is as much like an ideal voltage rail as possible. Ripple VR needs to be small, and that invites the use of a few modifications to single-phase AC-DC converters, as represented by figures 9.4-5(a) and 9.4-5(b)
and is V (^) P = VS – V (^) D for HWR (9.4-11a) V (^) P = VS – 2VD for FWR (9.4-11b)
And (^) VL t VP 0. 5 VR (9.4-12)
In spite of this exposition, it is more likely that the fat knobs that resemble a wall plug do not pause at one of the above options. Most of the time they will contain an extra diode that will almost ensure that the output is flat. This diode component is called a Zener diode, so named after the Zener breakdown effect (Clarence M. Zener) which occurs when the junction is alloyed with heavy doping on both sides so that the built-in E-field is close to the breakdown limit. A typical I-V response is shown by figure 9.4-7(b)
Figure 9.4-7(a) Zener diode component. When V (^) R exceeds V (^) Z the junction breaks down. Figure 9.4-7(b) Zener diode I-V response (spice rendition of 1n750, V (^) Z = 4.3V zener diode.
By adjustment of the doping levels, zener breakdown voltages from 1.8V to 90V are not uncommon.
The selection of breakdown voltages provides a ready candidate for regulation of the voltage level. Zener diodes with V (^) Z > 5.0V have a positive temperature coefficient on the order of +3mV/o^ C (although it varies with V (^) Z ) , so it usually is placed in series with a forward-biased junction diode as is indicated by the figure. The temperature coefficient for the diode junction is typically on the order of -3mV/o^ C, and so the effects will cancel and the output will be reasonably well-behaved over a large range of current variations.
A typical Zener application is represented by example 9.4-1.
EXAMPLE 9.4-1: The circuit shown represents a simple automotive voltage-reduction circuit with a variable source 12 < Vbat < 15V and a 300mW load that may either be ON or OFF. The Zener diode is a 1n754 ( VZ = 6.8V) and the junction diode has forward voltage drop V (^) D = 0.7V.
Find: (a) drop-down resistance R (^) S such that the Zener diode set always remains in reverse breakdown (maintains regulation) with current minimum of 5 mA and (b) (1) the worst-case power dissipated in the Zener diode and (2) in the resistance Rs.
SOLUTION: The voltage across the load is V (^) L = VZ + VD = 6.8 + 0.7 = 7.5V So the current drawn by the application is I (^) L = PL/V (^) L = 300mW/7.5V = 40mA
Therefore the minimum current that must be supplied by the source
= I (^) L + IZ ( min ) = 40mA + 5mA = 45mA
Vbat(min) must be able to supply 45mA through R (^) S , which must then be
R (^) S = [ Vbat ( min ) – V (^) L ]/ I (^) S ( min ) = ( 12 – 7.5)/45mA = 0.1 k = 100
The worst-case power dissipated through the Zener diode is when Vbat = Vbat(max) and the load is OFF.
The current that flows through RS will be IS ( max ) = (15 – 7.5)/0.1k = 75 mA
All of this current will flow through the Zener diode when the application is OFF and therefore
P (^) L(worst) = 6.8V x 75mA = 510mW = 0.51W
Take note from the example that the Zener diode must always have a drop-down resistance, both because it is required that V (^) Z < V(source) and because the R (^) S is needed to limit the current through the zener diode.
This context is represented in a more typical use of a Zener diode in context with an AC-DC converter topology as shown by example 9.4-
EXAMPLE 9.4-2: For the FWR topology shown choose component values that will support a Zener regulated 240mW, 6V application from a 120V 60Hz power tap. Transformer turns ratio n 12 = 12:1. Assume all diode are Si power diodes ( V (^) D = 0.8V)
Figure E9.4-2 Full-wave rectifier AC-DC Zener-regulated charging plug.
(a) Determine V (^) C and V (^) P
