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6.012 Microelectronic Devices and Circuits
Formula Sheet for the Final Exam, Fall 2009
Parameter Values: Periodic Table:
q = 1.6 x 10
" 19 Coul
o
= 8.854 x 10
" 14 F / cm
r,Si
Si
" 12 F / cm
n i [ Si @ R. T ] $^10
10 cm
" 3
kT / q $ 0.025 V ; (^) ( kT / q ) ln10 $ 0.06 V
1 μ m = 1 x 10
" 4 cm
III IV V
B C N
Al Si P
Ga Ge As
In Sn Sb
Drift/Diffusion: Electrostatics:
Drift velocity : s x
= ±μ m
E
x
Conductivity : " = q μ e
n + μ h ( p )
Diffusion flux : F m
= # D
m
$ C
m
$ x
Einstein relation :
D
m
μ m
kT
q
dE ( x )
dx
= #( x ) E ( x ) =
#( x ) dx $
d &( x )
dx
= E ( x ) &( x ) = % E ( x ) dx $
d
2 &( x )
dx
2
= #( x ) &( x ) = %
#( x ) dxdx $$
The Five Basic Equations:
Electron continuity :
" n ( x , t )
" t
q
" J
e
( x , t )
" x
= g L
( x , t ) # n ( x , t ) $ p ( x , t ) # n i
2
[ ] r ( T )
Hole continuity :
" p ( x , t )
" t
q
" J
h
( x , t )
" x
= g L
( x , t ) # n ( x , t ) $ p ( x , t ) # n i
2
[ ] r ( T )
Electron current density : J e
( x , t ) = q μ e
n ( x , t ) E ( x , t ) + qD e
" n ( x , t )
" x
Hole current density : J h
( x , t ) = q μ h
p ( x , t ) E ( x , t ) # qD h
" p ( x , t )
" x
Poisson's equation :
" E ( x , t )
" x
q
%
p ( x , t ) # n ( x , t ) + N d
( x ) # N a
( x ) [ ]
Uniform doping, full ionization, TE
n - type, N d
>> N
a
n o
" N
d
# N
a
$ N
D
, p o
= n i
2 n o
n
kT
q
ln
N
D
n i
p - type, N a
>> N
d
p o
" N
a
# N
d
$ N
A
, n o
= n i
2 p o
p
kT
q
ln
N
A
n i
Uniform optical excitation, uniform doping
n = n o
n ' p = p o
p ' n ' = p '
dn '
dt
= g l
( t ) " p o
Low level injection, n',p' << p o
dn '
dt
n '
min
= g l
( t ) with # min
$ p o ( r )
" 1
Flow problems (uniformly doped quasi-neutral regions with quasi-static excitation and low
level injection; p-type example):
Minority carrier excess :
d
2 n '( x )
dx
2
n '( x )
L
e
2
D
e
g L
( x ) L e
# D
e
$ e
Minority carrier current density : J e
( x ) % qD e
dn '( t )
dx
Majority carrier current density : J h
( x ) = J Tot
" J
e
( x )
Electric field : E x
( x ) %
q μ h
p o
J
h
( x ) +
D
h
D
e
J
e
( x )
Majority carrier excess : p '( x ) % n '( x ) +
,
q
dE x
( x )
dx
Short base, infinite lifetime limit:
Minority carrier excess :
d
2 n '( x )
dx
2
D
e
g L
( x ), n '( x ) " #
D
e
g L
( x ) dxdx $$
Non-uniformly doped semiconductor sample in thermal equilibrium
d
2 "( x )
dx
2
q
n i
e
q " ( x ) kT $ e
$ q " ( x ) kT
[ ]
$ N
d
( x ) $ N a [ ( x )] { }
n o
( x ) = n i
e
q " ( x ) kT , p o
( x ) = n i
e
$ q " ( x ) kT , p o
( x ) n o
( x ) = n i
2
Depletion approximation for abrupt p-n junction:
"( x ) =
_qN
Ap_
qN Dn
for
for
for
for
x < # x p
_x
p_
< x < 0
0 < x < x n
x n
< x
N
Ap
x p
= N
Dn
x n
( b
n
p
kT
q
ln
N
Dn
N
Ap
n i
2
w ( v AB
Si
( b
_v
AB_ ( )
q
N
Ap
+ N
( (^) Dn )
N
Ap
N
Dn
E
pk
2 q ( b
_v
AB_ ( )
Si
N
Ap
N
Dn
N
Ap
+ N
( (^) Dn )
q DP
( v AB
) = # AqN Ap
x p
v AB ( ) =^ # A^^2 q * Si
( b
_v
AB_ ( )
N
Ap
N
Dn
N
Ap
+ N
( (^) Dn )
Ideal p-n junction diode i-v relation:
n (- x p
n i
2
N
Ap
e
qvAB / kT , n '(- x p
n i
2
N
Ap
e
qvAB / kT " 1 ( ) ; p ( x n
n i
2
N
Dn
e
qvAB / kT , p '( x n
n i
2
N
Dn
e
qvAB / kT " 1 ( )
i D
= Aq n i
2
D
h
N
Dn
w n , eff
D
e
N
Ap
w p , eff
( e
qv AB / kT
w m
" x m
if L m
w m
L
m
tanh w m
" x m ( ) L m [ ] if^ L m
~ w m
L
m
if L m
<< w m
q Q NR, p - side
= Aq n '( x ) dx ,
q QNR , n - side
= Aq p '( x ) dx , Note : p '( x ). n '( x ) in QNRs
x n
w n
Large Signal Model for MOSFETs Operated below Threshold (weak inversion):
(n-channel) Only valid for for v GS
≤ V
T
, v DS
≥ 0, v BS
i G
( v GS
, v DS
, v BS
) = 0 , i B
( v GS
, v DS
, v BS
i D , s # t
( v GS
, v DS
, v BS
) " I
S , s # t
e
q v GS
_V
T_ ( v BS { )} n^ kT^ 1 # e
_qv
DS_ / kT
where I S , s # t
W
2 L
μ e
kT
q
2
Si
qN A
p
_v
BS_
K
o
V
t
2
p
_v
BS_
with V t
kT
q
, K
o
W
L
μ e
C
ox
, - $
Si
qN A
C
ox
, n " 1 +
p
_v
BS_
Large Signal Model for MOSFETs Reaching Velocity Saturation at Small v DS
(n-channel) Only valid for v BS
≤ 0, v DS
≥ 0. Neglects v DS
/2 relative to (v GS
-V
T
Saturation model : s y
( E
y
) = μ e
E
y
if E y
" E
crit
, s y
( E
y
) = μ e
E
crit
_s
sat_
if E y
$ E
crit
i G
( v GS
, v DS
, v BS
) = 0 , i B
( v GS
, v DS
, v BS
i D
( v GS
, v DS
, v BS
0 for v GS
& V
T
( ) <^0 <^ v
DS
W s sat
C
ox
v GS
& V
T
( v BS
[ )] 1 +^ '^ v
DS
crit
( L )
[ ]
for 0 < v GS
& V
T
( ),^ (
crit
L < v DS
W
L
μ e
C
ox
v GS
& V
T
( v BS
[ )] v
DS
for 0 < v GS
& V
T
( ),^ v
DS
crit
L
with ' # 1 V A
CMOS Performance
Transfer characteristic:
In general : V LO
= 0 , V
HI
= V
DD
, I
ON
= 0 , I
OFF
Symmetry : V M
V
DD
and NM LO
= NM
HI
" K
n
= K
p
and V Tp
= V
Tn
Minimum size gate : L n
= L
p
= L
min
, W
n
= W
min
, W
p
= μ n
μ
( p )
W
n
or W p
= s sat , n
s
( sat , p )
W
[ n ]
Switching times and gate delay (no velocity saturation):
" Ch arg e
Disch arg e
2 C
L
V
DD
K
n
V
DD
# V
Tn
[ ]
2
C
L
= n W n
L
n
+ W
p
L
( p )
C
ox
= 3 nW min
L
min
C
ox
assumes μ e
= 2 μ h
" Min. Cycle
Ch arg e
Disch arg e
12 nL min
2 V DD
μ e
V
DD
# V
Tn
[ ]
2
Dynamic power dissipation (no velocity saturation):
P
dyn @ f max
= C
L
V
DD
2 f max
C
L
V
DD
2
Min. Cycle
μ e
W
min
ox
V
DD
V
DD
% V
Tn
[ ]
2
t ox
L
min
PD
dyn @ f max
P
dyn @ f max
InverterArea
P
dyn @ f max
W
min
L
min
μ e
ox
V
DD
V
DD
% V
Tn
[ ]
2
t ox
L
min
2
Switching times and gate delay (full velocity saturation):
Ch arg e
Disch arg e
C
L
V
DD
W
min
s sat
C
ox
V DD
# V
Tn [ ]
C
L
= n W n
L
n
+ W
p
L
( (^) p )
C
ox
= 2 nW min
L
min
C
ox
assumes s sat , e
= s sat , h
Min. Cycle
Ch arg e
Disch arg e
4 nL min
V
DD
s sat
V
DD
# V
Tn [ ]
Dynamic power dissipation per gate (full velocity saturation):
P
dyn @ f max
= C
L
V
DD
2 f max
C
L
V
DD
2
Min. Cycle
s sat
W
min
$ ox
V
DD
V
DD
% V
Tn [ ]
t ox
PD
dyn @ f max
P
dyn @ f max
InverterArea
P
dyn @ f max
W
min
L
min
s sat
$ ox
V
DD
V
DD
% V
Tn [ ]
t ox
L
2
Static power dissipation per gate
P
static
= V
DD
I
D , off
" V
DD
W
min
L
min
μ e
V
t
2
Si
qN A
2 V
BS
e
$ V { (^) T } nV t
PD
static
P
static
Inverter Area
V
DD
L
min
2
μ e
V
t
2
Si
qN A
2 V
BS
e
$ V { (^) T } nV t
CMOS Scaling Rules - Constant electric field scaling
Scaled Dimensions : L min
" L
min
s W " W s t ox
" t ox
s N A
" s N A
Scaled Voltages : V DD
" V
DD
s V BS
" V
BS
s
Consequences : C ox
" sC ox
K " sK V T
" V
T
s
" # _s P
dyn_
" P
dyn
s
2 PD dyn @ f max
" PD
dyn @ f max
PD
static
" s
2 e
( s $ 1 ) V T s n V t PD static
Device transit times
Short Base Diode transit time : " b
w B
2
2 D
min, B
w B
2
2 μ min, B
V
thermal
Channel transit time, MOSFET w.o. velocity saturation : " Ch
L
2
μ Ch
V
GS
# V
T
Channel transit time, MOSFET with velocity saturation : " Ch
L
s sat
Single transistor analog circuit building block stages Note: g l ≡ g sl
MOSFET
Voltage
gain, A
v
Current
gain, A
i
Input
resistance, R
i
Output
resistance, R
o
Common source "
g
m
g
o
+ g
l [ ]
= " g
m
r
l
'
( )
# # r
o
g
o
Common gate * g
m
+ g
mb [ ] r l
'
g
m
+ g
mb [ ]
* r
o
g
m
+ g
mb
+ g
o [ ]
g
t
Source follower
g
m [ ]
g
m
+ g
o
+ g
l [ ]
g
m
+ g
o
+ g
l [ ]
g
m
Source degeneracy
(series feedback)
r
l
R
F
# # * r
o
Shunt feedback "
g
m
" G
F [ ]
g
o
+ G
F [ ]
* " g
m
R
F
g
l
G
F
G
F
1 " A
v [ ]
r
o
|| R
F
g
o
+ G
F [ ]
BIPOLAR
Voltage
gain, A v
Current
gain, A i
Input
resistance, R i
Output
resistance, R o
Common emitter "
g m
g o
" _g
m_
r l
'
( )
$ g l
g o
r %
r o
g o
Common base
g m
g o
_g
m_
r l
'
( )
r %
[^ $ +^1 ]
#[ $ + (^1) ] r o
Emitter follower
g m
g m
$ g l
g o
$ r
%
+[ $ + (^1) ] r l
' r t
[^ $ +^1 ]
Emitter degeneracy # "
r l
R
F
$ # r
%
+[ $ + (^1) ] R F
_r
o_
Shunt feedback "
g m
" G
F [ ]
g o
+ G
F [ ]
" _g
m_
R
F
g l
G
F
g %
+ G
F
1 " A
v [ ]
r o
|| R
F
g o
+ G
F
OCTC/SCTC Methods for Estimating Amplifier Bandwidth
OCTC estimate of " HI
HI
i [ ]
$ 1
i
%
= R
i
C
i
i
%
with R i
defined as the equivalent resistance in parallel with C i
with all other parasitic
device capacitors (C π 's, C μ 's, C gs 's, C gd 's, etc.) open circuited.
SCTC estimate of " LO
LO
j
j
$
= R
j
C
[ (^) j]
% 1
j
$
with R j defined as the equivalent resistance in parallel with C j with all other baising
and coupling capacitors (C Ι
's, C O
's, C E
's, C S
's, etc.) short circuited.
Difference- and Common-mode signals
Given two signals, v 1 and v 2 , we can decompose them into two new signals, one (v C
that is common to both v 1 and v 2 , and the other (v D ) that makes an equal, but opposite
polarity contribution to v 1 and v 2
v D
" v 1
v
2
and v C
v 1
[ ]
$$ % v 1
= v C
v D
and v 1
= v C
v D
Short circuit current gain unity gain frequency, f T
" t
g m
C
gs
= 3 μ Ch
V
GS
$ V
T
( ) 2 L
2 = 3 s Ch
2 L MOSFET, no vel. sat.
g m
C
gs
= W s sat
C
ox
W LC ox
= s sat
L MOSFET, w. vel. sat.
g m
C
%
+ C
; lim I c &'
g m
C
%
+ C
[ (^ μ)]
# 2 D
min, B
w B
2 BJT, large I C
/ tr
Revised 12/9/
