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MOSFET Circuit Analysis Problems - Complete
Report
Shaik Sharjidh
Electrical engineering IIT Tirupati
Index Terms—MOSFET, circuit analysis, gate capacitance, threshold voltage, AC analysis, HSPICE simulation, semiconduc- tor devices
I. INTRODUCTION
This report provides detailed solutions to MOSFET circuit analysis problems covering fundamental device characteristics and circuit applications. The analysis focuses on 50nm pro- cess technology and includes both theoretical derivations and practical simulation approaches using HSPICE.
II. PROBLEM 6.1: AC ANALYSIS OF MOSFET CAPACITOR CIRCUIT
A. Problem Statement
Plot the magnitude and phase of vout (AC) in the circuit shown in Figure 6.20. The MOSFET is fabricated using a 50 nm CMOS process and operates in strong inversion.
Fig. 1. MOSFET Capacitor Circuit from Problem 6.
B. Circuit Analysis
Given Parameters:
- Input AC voltage: 1 mV
- DC gate bias: 500 mV
- Series resistor: 250 kΩ
- W/L = 100
- Process node: 50 nm Circuit Configuration: The circuit behaves as an RC low- pass filter. The gate receives the input signal via a 250 kΩ resistor. Both drain and source are grounded. The output volt- age vout is measured at the gate, across the gate capacitance of the MOSFET.
C. Theoretical Analysis
MOSFET as a Capacitor: In strong inversion, with both drain and source at ground, the MOSFET behaves like a capacitor between gate and channel.
- Gate Capacitance:
- Cox ≈ 8. 6 fF/μm^2 for 50 nm technology
- W/L = 100, choose L = 50 nm ⇒ W = 100 × 50 nm = 5 μm Intrinsic gate capacitance:
Cintrinsic = Cox · W · L = 8. 6 fF μm^2
· 5 μm · 0. 05 μm = 2. 15 fF (1) Overlap capacitance:
Coverlap ≈ 2 · Cov · W = 2 · 0. 3
fF μm · 5 μm = 3. 0 fF (2)
Total gate capacitance:
Cgate,total = Cintrinsic+Coverlap = 2. 15 fF+3. 0 fF = 5. 15 fF (3)
- RC Low-Pass Filter Analysis:
H(jω) =
1 + jωRC
|H(jω)| =
p 1 + (ωRC)^2
, ∠H(jω) = − tan−^1 (ωRC) (5) Cutoff frequency:
f− 3 dB =
2 πRC
2 π · 250 · 103 · 5. 15 · 10 −^15
≈ 124 MHz (6) D. HSPICE Simulation
- Netlist Code: .model NMOS NMOS (LEVEL=1 VTO=0.4 KP=200e-6 LAMBDA=0.1)
VIN IN 0 AC 1m DC 0.5V RG IN G 250k M1 0 G 0 0 NMOS W=5u L=50n
.AC DEC 100 1 1G .PRINT AC VM(G) VP(G) .OPTIONS POST= .END
- Simulation Notes:
- Frequency range: 1 Hz to 1 GHz
- Output node: G (gate)
- Expect a low-pass filter response due to RC behavior
E. Expected Results
Magnitude Response:
- Unity gain at low frequency: |H(jω)| ≈ 1
- − 3 dB point at f− 3 dB ≈ 124 MHz
- Roll-off: − 20 dB/decade beyond cutoff Phase Response:
- 0° at low frequencies
- − 45 ◦^ at cutoff frequency
- Approaches − 90 ◦^ at high frequencies
F. Simulation Output
Fig. 2. AC magnitude response of vout from HSPICE simulation
Fig. 3. AC phase response of vout from HSPICE simulation
G. Discussion
The simulated magnitude and phase response match the expected RC low-pass filter behavior. At low frequencies, the capacitive reactance is high, and the signal appears entirely at the gate. At higher frequencies, the gate capacitance shorts the input, attenuating vout. The phase shift confirms first-order lag dynamics.
III. PROBLEM 6.2: MOSFET AS CAPACITOR IN STRONG
INVERSION
A. Problem Statement
If a MOSFET is used as a capacitor in strong inversion where the gate is one electrode and the source/drain change the capacitance, analyze the overlap capacitance.
B. Theoretical Analysis MOSFET Capacitances: When operating in strong inver- sion, the MOSFET exhibits several capacitances: Gate-Channel Capacitance (Cgc):
Cgc = W × L × Cox (7)
Overlap Capacitances:
Gate-Source overlap: Cgso = W × Lov × Cox (8) Gate-Drain overlap: Cgdo = W × Lov × Cox (9)
Where Lov is the overlap length (typically 10-20% of gate length). Effect of Source/Drain Connection: When source and drain are connected together, the effective capacitance be- comes: Ctotal = Cgc + Cgso + Cgdo (10)
Capacitance Value: For typical 50 nm process:
- Cox ≈ 7 fF/μm^2
- For W/L = 100 with L = 50 nm: W = 5 μm
- Cgc = 5μm × 0. 05 μm × 7 fF/μm^2 = 1. 75 fF
- Overlap capacitances add approximately 10-20% more
IV. PROBLEM 6.3: SUBTHRESHOLD OPERATION
A. Problem Statement When the MOSFET is operating in the accumulation region, analyze the gate capacitance.
B. Theoretical Analysis Accumulation Region Operation:
- Occurs when VGS < VF B (flatband voltage)
- Majority carriers accumulate at the semiconductor surface
- No depletion region exists Gate Capacitance in Accumulation:
Cgate = Cox =
ϵox × A tox
Where:
- ϵox = oxide permittivity
- A = gate area = W × L
- tox = oxide thickness Characteristics:
- Capacitance is maximum and equals Cox
- Independent of bias voltage in deep accumulation
- No voltage dependence unlike inversion/depletion regions
V. PROBLEM 6.4: OXIDE THICKNESS CALCULATION
A. Problem Statement If the oxide thickness of a MOSFET is 40 ˚A, what is Cox?
Calculation Example: For NA = 10^16 cm−^3 :
ϕF = 26 mV × ln
1. 5 × 1010
= 26 mV × ln(6. 67 × 105 ) (27) = 347 mV (28)
ϕs = 2 × 347 mV = 694 mV (29)
Result: The electrostatic potential at the interface is approx- imately 0.7V.
IX. PROBLEM 6.8: THRESHOLD VOLTAGE WITH DIFFERENT VGS
A. Problem Statement
Repeat Problem 6.5 to get a threshold voltage of 0.8V.
B. Design Analysis
Target: VT H = 0. 8 V Method 1: Adjust Oxide Thickness
VT H 0 = ϕms −
Qox Cox
Assuming ϕms = − 0. 95 V, ϕF = 0. 35 V:
0 .8 = − 0. 95 −
Qox Cox
Qox Cox
= − 0 .95 + 0. 7 − 0 .8 = − 1. 05 V (32)
Required: Negative oxide charge of Qox/Cox = − 1. 05 V Method 2: Adjust Doping Concentration
VT H = VT H 0 + γ
p 2 ϕF (33)
Where γ =
√ 2 qϵ siNA Cox For VT H = 0. 8 V with VT H 0 = 0. 4 V:
0 .8 = 0.4 + γ
2 × 0. 35 (34)
γ
γ =
= 0. 478 V^1 /^2 (36)
Required doping:
NA =
γ^2 C ox^2 2 qϵsi
≈ 5. 2 × 1016 cm−^3 (37)
Design Solution: Use substrate doping of NA = 5. 2 × 1016 cm−^3
X. PROBLEM 6.9: SODIUM CONTAMINATION EFFECT
A. Problem Statement
What happens to the threshold voltage in Problem 6.8 if sodium contamination of 100 × 109 sodium ions/cm^2 is present at the oxide-semiconductor interface?
B. Analysis Effect of Sodium Contamination: Sodium ions (Na+) trapped at the oxide-semiconductor interface act as fixed positive charges. These charges induce an electric field that opposes the gate voltage, effectively reducing the threshold voltage. Step 1: Calculate Fixed Charge Density
Qf = q ×NN a = 1. 6 × 10 −^19 × 100 × 109 = 1. 6 × 10 −^8 C/cm^2 (38) Step 2: Use Oxide Capacitance in Consistent Units From Problem 6.4, we have:
Cox = 8. 63 fF/μm^2 = 8. 63 × 10 −^3 F/m^2
Convert to F/cm^2 :
Cox = 8. 63 × 10 −^3 × (10−^2 )^2 = 8. 63 × 10 −^7 F/cm^2 (39)
Step 3: Calculate Threshold Voltage Shift
∆VT H = −
Qf Cox
1. 6 × 10 −^8
8. 63 × 10 −^7
≈ − 0. 0185 V (40)
C. Result
- Original threshold voltage: VT H = 0. 8 V
- Threshold shift due to sodium: ∆VT H ≈ − 18. 5 mV
- New threshold voltage: VT H,new = 0. 8 − 0. 0185 ≈
- 7815 V
- The device remains enhancement-mode, but threshold is slightly reduced.
XI. PROBLEM 6.10: AVAILABLE CHARGE ANALYSIS A. Problem Statement How much charge (enhanced electrons) is available under the gate for conducting a drain current at the drain-channel interface when the MOSFET is operating in strong inversion?
B. Analysis Inversion Charge Density: In strong inversion, the mobile electron charge per unit area is:
Qi = Cox(VGS − VT H ) (41)
Total Available Charge:
Qtotal = Qi × W × L = Cox(VGS − VT H ) × W × L (42)
At Drain End: Due to channel length modulation and ve- locity saturation, the effective charge available for conduction is:
Qef f = Cox
VGS − VT H −
VDS
× W × L (43)
Example Calculation: For VGS = 1V, VT H = 0. 4 V, W/L = 100, L = 50nm:
Qi = 8. 63 fF/μm^2 × (1. 0 − 0 .4)V = 5. 18 fC/μm^2 (44) Qtotal = 5. 18 fC/μm^2 × 5 μm × 0. 05 μm = 1. 295 fC (45)
XII. PROBLEM 6.11: PMOS DEVICE EQUATION
DERIVATION
A. Problem Statement
Show the details of the derivation for Eq. (6.33) for the PMOS device.
B. Derivation
Starting Point - Basic MOSFET Equation: For NMOS:
ID = μnCox
W
L
(VGS − VT H )VDS −
V DS^2
For PMOS Device: The derivation follows the same physics but with opposite polarity. Step 1: Charge Analysis Inversion charge in PMOS (holes):
Qi = −Cox(VSG − |VT H |) (47)
Step 2: Current Density Current density due to hole drift:
Jp = Qi × μp × Ey (48)
Step 3: Electric Field
Ey = −
dV dy
Step 4: Current Integration
ID = W
Z L
0
Jp dy = W
Z L
0
Qiμp
dV dy
dy (50)
Step 5: Substitution and Integration
ID = −W μp
Z VD
VS
Cox(VSG − |VT H |) dV (51)
Step 6: Final Result
ID = μpCox
W
L
(VSG − |VT H |)|VSD| −
|VSD|^2
Alternative Form: Using conventional notation with nega- tive voltages:
ID = μpCox
W
L
(|VGS | − |VT H |)|VDS | −
|VDS |^2
This is Equation (6.33) for PMOS devices.
XIII. PROBLEM 6.12: SMALL-SIGNAL CHANNEL
RESISTANCE
A. Problem Statement
Using Eq. (6.35), estimate the small-signal channel resis- tance of a MOSFET operating in the triode region.
B. Analysis Small-Signal Channel Resistance:
rds =
∂VDS
∂ID (^) VGS =constant
From Triode Region Equation:
ID = μnCox
W
L
(VGS − VT H )VDS −
V DS^2
Taking the Derivative: ∂ID ∂VDS
= μnCox
W
L
[(VGS − VT H ) − VDS ] (56)
Small-Signal Resistance:
rds =
μnCox WL (VGS − VT H − VDS )
For Small VDS (Deep Triode):
rds ≈
μnCox WL (VGS − VT H )
Numerical Example: For VGS − VT H = 0. 6 V, W/L = 100, μn = 400 cm^2 /V·s, Cox = 8. 63 fF/μm^2 :
rds =
400 × 8. 63 × 10 −^3 × 100 × 0. 6
XIV. PROBLEM 6.13: PARALLEL MOSFET CONNECTION
A. Problem Statement Show that the parallel connection of MOSFETs behaves as a single MOSFET with width equal to the sum of individual MOSFET widths.
B. Proof Parallel Connection Analysis: Consider n MOSFETs in parallel, each with width Wi and same length L. Individual Currents:
IDi = μCox Wi L
(VGS − VT H )VDS −
V DS^2
Total Current:
ID,total =
X
IDi =
X
μCox
Wi L
(VGS − VT H )VDS −
V DS^2
Factoring Common Terms:
ID,total = μCox
L
(VGS − VT H )VDS −
V DS^2
×
X
Wi (62) Equivalent Single MOSFET:
ID,total = μCox
Weq L
(VGS − VT H )VDS −
V DS^2
Where:
Weq =
X
Wi = W 1 + W 2 +... + Wn (64)
Current-Voltage Relationship: The I-V characteristics of the series combination match those of a single MOSFET with length 2L. Conclusion: Series connection of two identical MOSFETs behaves as a single MOSFET with twice the individual length.
XVII. SUMMARY This report provides comprehensive solutions to all MOS- FET problems (6.1-6.15), including:
- AC analysis with HSPICE simulation setup
- Capacitance analysis in different operating regions
- Threshold voltage calculations and contamination effects
- Mathematical derivations for PMOS equations
- Small-signal parameter calculations
- Circuit analysis for parallel and series MOSFET connec- tions Each solution includes relevant formulas, derivations, and numerical examples where applicable. The HSPICE code provided for Problem 6.1 can be adapted for other simulation requirements in problems 6.12-6.15.
XVIII. KEY FINDINGS AC Analysis Results:
- Cutoff frequency: approximately 296 MHz
- First-order low-pass filter behavior
- Unity gain at DC with -20 dB/decade roll-off Capacitance Analysis:
- Gate capacitance: approximately 2.15 fF for W/L = 100 devices
- Capacitance saturates at Cox in strong inversion
- Accumulation region provides maximum capacitance Threshold Voltage Effects:
- Significant shift due to contamination (-1.85V for sodium contamination)
- Potential for depletion mode operation
- Surface potential of 0.7V at threshold condition Device Modeling:
- Parallel connection: effective width = sum of individual widths
- Series connection: effective length = sum of individual lengths
- Bottom MOSFET in series cannot achieve saturation
XIX. CONCLUSION The analysis demonstrates fundamental MOSFET behavior across various operating regions and circuit configurations. The theoretical predictions align with expected device physics, providing a solid foundation for advanced MOSFET circuit design and analysis. The HSPICE simulation frameworks established here can be extended for more complex circuit analysis and optimization tasks.
