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Some Important Questions Regarding Computer Organization And Architecture
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Types Of RAM:- SRAM: Static Random Access Memory (SRAM) Data is stored in transistors and requires a constant power flow. Because of the continuous power, SRAM doesn’t need to be refreshed to remember the data being stored. SRAM is called static as no change or action i.e. refreshing is not needed to keep the data intact. It is used in cache memories. Characteristics of Static RAM
action(change is continuously happening) i.e. refreshing is needed to keep the data intact. It is used to implement main memory. Characteristics of Dynamic RAM
Q. Design a 4 bit combinational circuit decrementer using four full adders. Ans: What is 4 Bit Binary Decrementer? It subtracts 1 binary value from the existing binary value stored in the register or in other words we can simply say that it decreases the existing value stored in the register by 1. For any n- bit binary decrementer, ‘n’ refers to the storage capacity of the register which needs to be decremented by 1. So we require ‘n’ number of full adders. Thus, in case of 4 bit binary decrementer we require 4 full adders. Explanation: Working: It consists of 4 full adders, connected one after the other. Each full adder has 3 inputs (carry input, 1, A) and 2 outputs (carry output and S)Afull adderbasic consist of 2 half adders and an OR gate.The carry(C) from previous full adder is propagated to the next full adder. So carry output from one full adder becomes one of the three input of the next full adder.It follows the concept of 2’s complement, so we take 1 as input in all 4 full adder as seen from the above diagram.So we add 1111 in order to subtract 1. Reason for adding 1111: This is because our main motive is to subtract 1 which in 4 bit representation is 0001Representing it in 1’s complement will give: 1110Representing it in 2’s complement (adding 1 to 1’s complement) will give: 1111This is the reason why input 1111 is given to get a decremented output in 4 bit binary decrementer.
In 4 bit representation In 1's complement In 2's complement 1 -------------------------> 0001 ----------------------> 1110 ---------------------> 1111
Q. How to implement full adders using half adders? Ans: Implementation of full adder from half adders is possible because the half adders add two 1-bit inputs in full adder we add three 1-bit inputs. To obtain a full adder from a half adder we take the first two inputs and add them and use the sum and carry outputs and the third input to get the final sum and carry output of the full adder. In this article, we will explore half adders, and full adders and implement full adders using half adders. What is Half Adder? Half adder is a combinational circuit that is used to add two 1-bit inputs to generate two outputs sum and carry. The sum in half adder is given by XORing both the inputs. The carry in the half adder is given by the product of both inputs. Half Adders are used in the Various Digital Systems Where Addition of Binary Numbers is Required Such as Arithmetic Circuits, Digital Calculators, Microcontrollers and Processors, Communication systems and Control Systems.
Block Diagram for Half Adder Below is the block diagram for half adder.
What is Full Adder? Full adder is a combinational circuit that is used to add three 1-bit inputs to generate two outputs sum and carry. The sum in full adder is given by XORing all the inputs. The carry in the full adder is given by sum of product of two inputs. Full Adders are important component in digital Circuit and are used in the ALUs (Arithmetic Logic Units),Binary Additions, Address decoding, Counters and Registers, Data Encryption and Decryption and Digital Signal Processing. Expression for Sum in Full Adder From the above truth table, the expression for sum S in half adder is: S = A ⊕ B ⊕C where, A, B and C are inputs and ⊕represents XOR operation.
Q. What is Von-Neumann bottleneck? How can it be reduced? Ans: Von Neumann Architecture: This architecture, named after John von Neumann, uses a single bus to transfer both data and instructions between the CPU and memory.
The Bottleneck: The problem arises because the CPU can process data much faster than it can receive it from memory, or send it back. This means the CPU is often idle, waiting for data or instructions to arrive, creating a performance bottleneck.
Impact: This bottleneck can limit the overall performance of a computer system, especially when dealing with large datasets or complex computations.
Solutions: To mitigate the Von Neumann bottleneck, various techniques have been developed, including:
Caching: Using faster, smaller memory (cache) to store frequently accessed data and instructions.
Parallel Processing: Employing multiple CPUs or processing units to perform tasks concurrently.
Alternative Architectures: Exploring non-Von Neumann architectures, such as Harvard architecture, which separates data and instruction memory.
What is the Von Neumann Bottleneck? - TechTarget The von Neumann bottleneck is a limitation on throughput caused by the standard personal computer architecture. The Q. What are the hazards in pipelining? Ans: Here's a breakdown of the different types of pipeline hazards: