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Combinational Logic Implementation, Lecture notes of Engineering

Information about decoders and TTL data sheets. It explains that a decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. The document also includes a Google search for TTL data sheets and a list of Medium Scale Integration ICs.

Typology: Lecture notes

2021/2022

Available from 12/22/2022

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Decoders 1
DECODERS
A decoder is a combinational circuit that
converts binary information from ninput lines to a
maximum of 2nunique output lines.
For each possible input combination, there are
2noutput lines only one output is asserted (equal
to 1).
The output whose value is equal to 1 represents
the minterm equivalent of the binary number
presently available in the input lines.
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a

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Decoders^

DECODERS

™A^ decoder

is a combinational circuit that converts binary information from

n^ input lines to a

maximum of

n^ 2 unique output lines.

™For each possible input combination, there are n^2 output lines only one output is asserted (equalto 1). ™The output whose value is equal to 1 representsthe minterm equivalent of the binary numberpresently available in the input lines.

Decoders^

2x4 DECODER

Decoders^

2x4 DECODER

2X4DECODER

D

X

D

Y

D2 D

E

Decoders^

2x4 DECODER

Decoders^

Decoders^

Decoders^

Medium Scale Integration ICs 74LS^

  • 1-of-8 Decoder/Demultiplexer 74LS
    • 1-Bit 8:1 MUX 74LS
      • 4-Bit 2:1 MUX 74LS
        • 4-bit Counter with Synchronous Clear 74LS
          • BCD Up/Down Counter 74LS
            • 4-Bit Up/Down Counter 74LS195A
              • Universal 4-bit Shift Register 74LS
                • Quad Set-Reset Latch

Decoders^

74LS

  • Four 2-Input ANDs 74LS
    • Four 2-Input ORs 74LS
      • 4-Bit Binary Adder 74LS
        • 4-Bit Magnitude Comparator 74LS
          • 2-Bit 4:1 MUX 74LS
            • Dual 2:4 Decoder/Demux 74LS
              • 4-bit Counter with Direct Clear 74LS
                • 4-Bit D-Type Register 74LS194A
                  • 4-Bit Shift Register 74LS
                    • 4-Bit Binary Full Adder with Fast Carry 74F - 4-Bit ALU

Decoders^

74LS

  • Dual 2:4 Decoder/Demux

Decoders^

DECODERS

™Some decoders are constructed with NANDgates. ™Decoders include one or more

enable

inputs to

control the circuit operation. ™A decoder with enable input can function as a demultiplexer

™A demultiplexer is a circuit that receivesinformation from a single line and directs it to onen^ of 2^

possible output lines.

Decoders^

74LS

  • Dual 2:4 Decoder/Demux

Decoders^

74LS

  • Dual 2:4 Decoder/Demux

Decoders^

Combinational Logic Implementation ™Since any Boolean function can beexpressed in Sum of Minterms (SOP), onecan use a decoder to generate the mintermsand an external OR gate to form the logicalsum.

Decoders^

Example 1

™A combinational circuit is specified bythe following three Boolean functions:F(A,B,C) =^1

Σm(1,4,7)

F(A,B,C) =^2

Σm(0,3,6)

F(A,B,C) =^3

Σm(0,4,6,7)

Design this circuit using a decoder andexternal NAND gates.