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Complex Instruction Set Computer (CISC)Complex Instruction Set Computer (CISC)
- Emphasizes doing more with each instruction.
- Motivated by the high cost of memory and hard disk
capacity when original CISC architectures were proposed:
- When M6800 was introduced: 16K RAM = $500, 40M hard disk = $ 55, 000
- When MC68000 was introduced: 64K RAM = $200, 10M HD = $5,
- Original CISC architectures evolved with faster, more
complex CPU designs, but backward instruction set compatibility had to be maintained.
- Wide variety of addressing modes:
- A number instruction modes for the location and number of
operands:
- The VAX has 0- through 3-address instructions.
- Variable-length or hybrid instruction encoding is used.
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Example CISC ISAs Example CISC ISAs
Motorola 680X0 Motorola 680X
18 addressing modes:
- Data register direct.
- Address register direct.
- Immediate.
- Absolute short.
- Absolute long.
- Address register indirect.
- Address register indirect with postincrement.
- Address register indirect with predecrement.
- Address register indirect with displacement.
- Address register indirect with index (8-bit).
- Address register indirect with index (base).
- Memory inderect postindexed.
- Memory indirect preindexed.
- Program counter indirect with index (8-bit).
- Program counter indirect with index (base).
- Program counter indirect with displacement.
- Program counter memory indirect postindexed.
- Program counter memory indirect preindexed.
Operand size:
- Range from 1 to 32 bits, 1, 2, 4, 8, 10, or 16 bytes.
Instruction Encoding:
- Instructions are stored in 16-bit words.
- the smallest instruction is 2- bytes (one word).
- The longest instruction is 5 words (10 bytes) in length.
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Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC)
- Focuses on reducing the number and complexity of instructions of the machine.
- Reduced number of cycles needed per instruction.
- Goal: At least one instruction completed per clock cycle.
- Designed with CPU instruction pipelining in mind.
- Fixed-length instruction encoding.
- Only load and store instructions access memory.
- Simplified addressing modes.
- Usually limited to immediate, register indirect, register
displacement, indexed.
- Delayed loads and branches.
- Prefetch and speculative execution.
- Examples: MIPS, HP-PA, UltraSpark, Alpha, PowerPC.
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RISC Instruction Set Architecture Example:RISC Instruction Set Architecture Example: MIPS R3000MIPS R
- Memory: Can address 2^32 bytes or 2^30 words (32-bits).
- Instruction Categories:
- Load/Store.
- Computational: ALU.
- Jump and Branch.
- Floating Point.
- Memory Management.
- Special.
- 3 Instruction Formats: all 32 bits wide:
R0 - R
PC
HI
LO
Registers
GPRs
R0 = 0
R-Type OP rs (^) rt rd sa funct
Load/Store, BranchI-Type:^ ALU^ OP^ rs^ rt^ immediate
J-Type: Jumps OP (^) jump target
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MIPS Register Usage/Naming Conventions MIPS Register Usage/Naming Conventions
- In addition to the usual naming of registers by $ followed with register
number, registers are also named according to MIPS register usage
convention as follows:
Register Number Name Usage Preserved on call?
$zero
$at
$v0-$v
$a0-$a
$t0-$t
$s0-$s
$t8-$t
$k0-$k
$gp
$sp
$fp
$ra
Constant value 0
Reserved for assembler
Values for result and
expression evaluation
Arguments
Temporaries
Saved
More temporaries
Reserved for operating system
Global pointer
Stack pointer
Frame pointer
Return address
n.a.
no
no
yes
no
yes
no
yes
yes
yes
yes
yes
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MIPS Addressing Modes/Instruction Formats MIPS Addressing Modes/Instruction Formats
Immediate op rs rt immed
- All instructions 32 bits wide
op rs rt immed
register
Displacement: Base+index
+
Memory
op rs rt immed
PC
PC-relative
Memory
op rs rt rd
register
Register (direct)
First Operand Second Operand Destination
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Instruction Example Meaning Comment and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR xor xor $1,$2,$3 $1 = $2 ⊕ $3 3 reg. operands; Logical XOR nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable
MIPS Logic/Shift Instructions Examples MIPS Logic/Shift Instructions Examples
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Instruction Comment sw 500($4), $3 Store word sh 502($2), $3 Store half sb 41($3), $2 Store byte
lw $1, 30($2) Load word lh $1, 40($3) Load halfword lhu $1, 40($3) Load halfword unsigned lb $1, 40($3) Load byte lbu $1, 40($3) Load byte unsigned
lui $1, 40 Load Upper Immediate (16 bits shifted left by 16)
MIPS data transfer instructions Examples MIPS data transfer instructions Examples
LUI R
R
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Details of The MIPS Instruction Set Details of The MIPS Instruction Set
- Register zero always has the value zero (even if you try to write it).
- Branch/jump and link put the return addr. PC+4 into the link register
(R31).
- All instructions change all 32 bits of the destination register (including
lui, lb, lh) and all read all 32 bits of sources (add, sub, and, or, …)
- Immediate arithmetic and logical instructions are extended as follows:
- logical immediates ops are zero extended to 32 bits.
- arithmetic immediates ops are sign extended to 32 bits (including
addu).
- The data loaded by the instructions lb and lh are extended as follows:
- lbu, lhu are zero extended.
- lb, lh are sign extended.
- Overflow can occur in these arithmetic and logical instructions:
- add, sub, addi
- it cannot occur in addu, subu, addiu, and, or, xor, nor, shifts, mult,
multu, div, divu
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Example: C Assignment To MIPS Example: C Assignment To MIPS
- Given the C assignment statement:
f = (g + h) - (i + j);
- Assuming the variables are assigned to MIPS registers as
follows: f: $s0, g: $s1, h: $s2, i: $s3, j: $s
add $s0,$s1,$s2 # $s0 = g+h add $t1,$s3,$s4 # $t1 = i+j sub $s0,$s0,$t1 # f = (g+h)-(i+j)
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Example: C Assignment With Variable Index To MIPS Example: C Assignment With Variable Index To MIPS
- For the C statement with a variable array index: g = h + A[i];
- Assume: g: $s1, h: $s2, i: $s4, base address of A[ ]: $s
- Steps:
- Turn index i to a byte offset by multiplying by four or by addition as
done here: i + i = 2i, 2i + 2i = 4i
- Next add 4i to base address of A
- Load A[i] into a temporary register.
- Finally add to h and put sum in g
- MIPS Instructions:
add $t1,$s4,$s4 # $t1 = 2*i
add $t1,$t1,$t1 # $t1 = 4*i
add $t1,$t1,$s3 #$t1 = address of A[i]
lw $t0,0($t1) # $t0 = A[i]
add $s1,$s2,$t0 # g = h + A[i]
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Example: C If Statement to MIPS Example: C If Statement to MIPS
if (i == j) f=g+h; else f=g-h;
- Assume the following MIPS register mapping:
f: $s0, g: $s1, h: $s2, i: $s3, j: $s
beq $s3,s4, True # branch if i==j
sub $s0,$s1,$s2 # f = g-h (false)
j Exit # go to Exit
True: add $s0,$s1,$s2 # f = g+h (true)
Exit:
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Example: C Less Than Test to MIPS Example: C Less Than Test to MIPS
if (g < h) go to Less
- Assume MIPS register mapping:
g: $s0, h: $s
slt $t0,$s0,$s1 **_# $t0 = 1 if
$s0<$s1 (g < h)_**
bne $t0,$zero, Less **_# goto Less
if $t0 != 0_**
... # (if (g < h)
Less:
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Example: C Case Statement To MIPS Example: C Case Statement To MIPS
- The following is a C case statement called switch: switch (k) { case 0: f=i+j; break; / k=0/** case 1: f=g+h; break; / k=1/** case 2: f=g–h; break; / k=2/** case 3: f=i–j; break; / k=3/** }
- Assume MIPS register mapping:
f: $s0, g: $s1, h: $s2, i: $s3, j: $s4, k: $s
- Method: Use k to index a jump address table in memory, and then jump via the value loaded.
- Steps:
- 1st test that k matches one of the cases (0<=k<=3); if not, the code exits.
- Multiply k by 4 to index table of words.
- Assume 4 sequential words in memory, base address in $t2, have addresses corresponding to labels L0, L1, L2, L3.
- Load a register $t1 with jump table entry address.
- Jump to address in register $t1 using jump register jr $t1.
