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Computer Organisation Architecture part 2, Exams of Computer Architecture and Organization

Chhattisgarh Swami Vivekanand Technical UniversityComputer Architecture and Organization

This is previous year paper for University exam

Typology: Exams

2023/2024

Available from 05/14/2024

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Unit 2
Q1. In a computer with 48 bit words , one bit is reserved for the sign . What will be
the range of fixed point integer number ?!
Ans;- In a computer with 48-bit words and one bit reserved for the sign, the
remaining 47 bits are available for representing the magnitude of the fixed-point
integer number. !
To determine the range of the fixed-point integer number, we need to consider how
the sign bit affects the range. With one bit for the sign, we have two possibilities:
positive (0) or negative (1). Therefore, the sign bit can represent values from -1 to
+1.!
For the magnitude, with 47 bits, we can represent numbers from 0 to (2^47) - 1.
The subtraction of 1 accounts for the fact that 0 is included in the range.!
Combining the sign bit and magnitude, we have the following range for the fixed-
point integer number:!
Positive Range: 0 to (2^47) - 1!
Negative Range: -1 to -((2^47) - 1)!
Therefore, the overall range for the fixed-point integer number in this computer is:!
-((2^47) - 1) to (2^47) - 1!
Q2. Describe the process to make the process of addition and subtraction by
2’s complement number faster ?
Ans:- To make the process of addition and subtraction by 2's complement
numbers faster, you can follow these steps:!
1. Familiarize yourself with the 2's complement representation: In 2's
complement representation, negative numbers are represented by taking the
complement of the positive number and adding 1 to it.!
2. Use bit-level operations: Bit-level operations, such as bitwise NOT (~),
bitwise AND (&), bitwise OR (|), and bitwise XOR (^), can be used to perform
arithmetic operations faster. These operations can be implemented efficiently
in hardware.!
3. Avoid unnecessary carry propagation: When performing addition or
subtraction, carry propagation across multiple bits can slow down the
process. One way to avoid unnecessary carry propagation is by performing
addition or subtraction on smaller subgroups of bits rather than the entire
number at once.!
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Unit 2

Q1. In a computer with 48 bit words , one bit is reserved for the sign. What will be the range of fixed point integer number? Ans;- In a computer with 48-bit words and one bit reserved for the sign, the remaining 47 bits are available for representing the magnitude of the fixed-point integer number. To determine the range of the fixed-point integer number, we need to consider how the sign bit affects the range. With one bit for the sign, we have two possibilities: positive (0) or negative (1). Therefore, the sign bit can represent values from -1 to +1. For the magnitude, with 47 bits, we can represent numbers from 0 to (2^47) - 1. The subtraction of 1 accounts for the fact that 0 is included in the range. Combining the sign bit and magnitude, we have the following range for the fixed- point integer number: Positive Range: 0 to (2^47) - 1 Negative Range: -1 to -((2^47) - 1) Therefore, the overall range for the fixed-point integer number in this computer is: -((2^47) - 1) to (2^47) - 1 Q2. Describe the process to make the process of addition and subtraction by 2’s complement number faster? Ans:- To make the process of addition and subtraction by 2's complement numbers faster, you can follow these steps:

  1. Familiarize yourself with the 2's complement representation: In 2's complement representation, negative numbers are represented by taking the complement of the positive number and adding 1 to it.
  2. Use bit-level operations: Bit-level operations, such as bitwise NOT (~), bitwise AND (&), bitwise OR (|), and bitwise XOR (^), can be used to perform arithmetic operations faster. These operations can be implemented efficiently in hardware.
  3. Avoid unnecessary carry propagation: When performing addition or subtraction, carry propagation across multiple bits can slow down the process. One way to avoid unnecessary carry propagation is by performing addition or subtraction on smaller subgroups of bits rather than the entire number at once.
  1. Utilize parallel processing: Modern processors have multiple cores or execution units that can perform operations in parallel. By utilizing parallel processing, you can perform multiple additions or subtract
  2. Optimize algorithms: Depending on the specific problem or scenario, there may be algorithms or techniques that can optimize addition and subtraction operations further. For example, techniques like Karatsuba multiplication or multi-level carry lookahead adders can be employed to speed up calculations.
  3. Utilize hardware acceleration: Some processors or specialized hardware can provide hardware acceleration for arithmetic operations. These hardware units are designed to perform addition and subtraction operations quickly and efficiently, offloading the workload from the main processor and improving overall performance. Q3. Explain Booth multiplication along with for 2’s complement number using flow chart and Example? Ans;- Booth's algorithm is a technique used for efficient multiplication of signed (2's complement) binary numbers. It reduces the number of partial products required for multiplication, resulting in faster computation. Here's an explanation of Booth multiplication along with a flowchart and an example: 1. Initialize : Start by initializing the multiplicand (M), multiplier (Q), and the product (P) registers. Also, initialize a counter (C) to track the number of iterations. Set the counter to the bit length of the multiplier. 2. Loop : Enter a loop that will repeat until the counter becomes zero. Inside the loop, perform the following steps: a. Check the last two bits of the multiplier (Q1Q0). This will determine the operation to be performed: - If Q1Q0 = 00 or 11: No operation is required; proceed to the next iteration. - If Q1Q0 = 10: Perform a subtraction operation. - If Q1Q0 = 01: Perform an addition operation. 3. b. Based on the operation determined in the previous step, perform the following actions: - If subtraction is required, add the multiplicand (M) to the product (P) register. - If addition is required, subtract the multiplicand (M) from the product (P) register. 4. c. Right-shift the product (P) and the multiplier (Q) registers by one bit, including the sign bit. This is equivalent to performing a division by 2, where
  1. Initialize: Set M = 1011, Q = 1101, P = 0000, C = 4 (bit length of the multiplier).
  2. Loop:
    • Iteration 1:
    • Q1Q0 = 01 -> Perform addition: P = P - M = 0000 - 1011 = 1101
    • Right-shift: P = 0110, Q = 1110
    • C = 3
    • Iteration 2:
    • Q1Q0 = 10 -> Perform subtraction: P = P + M = 0110 + 1011 = 0001
    • Right-shift: P = 0000, Q = 1111
    • C = 2 Q4. Evaluate the following by using Restoring Division : Divisor is 11 ans Divided is 1000. Ans:- To evaluate the division using the Restoring Division algorithm, follow these steps:
  3. Set the Divisor (D) to 11 and the Dividend (A) to 1000 (the number being divided).
  4. Determine the sign of the quotient (Q) and remainder (R) based on the signs of the Divisor and Dividend.
  5. Initialize the Quotient (Q) and Remainder (R) registers. Set Q to 0 and R to the absolute value of the Dividend.
  6. Repeat the following steps for the bit length of the Dividend: a. Left-shift Q and R by 1 bit, including the sign bit. This is equivalent to performing a multiplication by 2, where the sign bit remains unchanged. b. Subtract the Divisor (D) from R. If the result is negative, restore R by adding D back to it and set the least significant bit of Q to 0. If the result is non-negative, set the least significant bit of Q to 1. c. If the result from step b is negative, restore R by adding D back to it and set the least significant bit of Q to 0. If the result is non-negative, set the least significant bit of Q to 1.
  7. After completing the iterations, the Quotient (Q) will contain the result of the division. Let's perform the division using the Restoring Division algorithm: Divisor (D) = 11 Dividend (A) = 1000
  8. Initialize: Q = 0, R = 1000.
  1. Repeat for the bit length of the Dividend (4 times):
    • Iteration 1:
      • Q = 00 (left-shift Q)
      • R = 10000 (left-shift R)
      • Subtract D from R: R - D = 10000 - 11 = 01101 (non-negative)
      • Set Q0 to 1: Q = 01
    • Iteration 2:
      • Q = 010 (left-shift Q)
      • R = 11010 (left-shift R)
      • Subtract D from R: R - D = 11010 - 11 = 11011 (non-negative)
      • Set Q0 to 1: Q = 011
    • Iteration 3:
      • Q = 0110 (left-shift Q)
      • R = 110110 (left-shift R)
      • Subtract D from R: R - D = 110110 - 11 = 110111 (non-negative)
      • Set Q0 to 1: Q = 0111
    • Iteration 4:
      • Q = 01110 (left-shift Q)
      • R = 1101110 (left-shift R)
      • Subtract D from R: R - D = 1101110 - 11 = 1101111 (non- negative)
      • Set Q0 to 1: Q = 01111
  2. After the iterations, the Quotient (Q) is 01111, which represents the decimal value 15. Therefore, the result of dividing 1000 by 11 using the Restoring Division algorithm is 15. Q5.Explain the array multiplication of positive binary operands in brief? Ans:-Array multiplication is a technique used to multiply positive binary operands. It involves multiplying individual bits of the operands and summing the partial products to obtain the final result. Here's a brief explanation of the array multiplication process: 1. Operand Preparation : The two binary operands are prepared for multiplication by aligning them vertically, with the multiplier on top and the multiplicand below it. Leading zeros may be added to ensure the operands have the same length. 2. Bit-wise Multiplication : Starting from the rightmost bit (least significant bit) of the multiplier, multiply each bit of the multiplier with every bit of the multiplicand. This is done by performing AND operations between the corresponding bits.
  • Iteration 2:
  • Q1Q0 = 10 -> Perform subtraction: P = P + M = 0110 + 1101 = 0011
  • Right-shift: P = 0001, Q = 1110
  • C = 2
  • Iteration 3:
  • Q1Q0 = 11 -> No operation required
  • Right-shift: P = 0000, Q = 1111
  • C = 1
  • Iteration 4:
  • Q1Q0 = 11 -> No operation required
  • Right-shift: P = 0000, Q = 1111
  • C = 0 d. Final Result: The result is stored in the Product register (P), which is 0000. Therefore, the product of -9 and -13 is 0000 in 2's complement representation, equivalent to 0 in decimal. 1. Traditional Multiplication Method: a. Multiply the absolute values of the numbers: -9 * -13 = 9 * 13 = 117 b. Determine the sign of the result: Since both numbers are negative, the result will be positive. c. Final Result: The product of -9 and -13 is 117. Q7. Explain IEEE floating point number representation ans is operation for 32 bits? Ans:-IEEE floating-point number representation is a standardized format for representing real numbers in computers. The most commonly used format is the IEEE 754 standard, which defines the binary representation and arithmetic operations for floating-point numbers. The 32-bit format, known as single precision, consists of three components: sign bit, exponent, and significand (also called fraction or mantissa). Here's a breakdown of the IEEE 754 single precision floating-point format for 32 bits:
  1. Sign Bit (1 bit): The leftmost bit represents the sign of the number. 0 denotes a positive number, and 1 denotes a negative number.
  1. Exponent (8 bits): The next 8 bits represent the exponent of the number. It uses an excess-127 representation, meaning a bias of 127 is added to the true exponent. The exponent can range from -126 to +127.
  2. Significand (23 bits): The remaining 23 bits represent the significand or fraction part of the number. It stores the fractional part of the number with a binary point. The significand bits are normalized, meaning the leftmost bit is always 1, which is not explicitly stored. The IEEE 754 format supports both normalized and denormalized numbers. Normalized numbers have an implicit leading 1 in the significand, while denormalized numbers have a leading 0 and represent values close to zero. Operations on IEEE 754 single precision floating-point numbers include addition, subtraction, multiplication, division, and square root. These operations follow specific rules and algorithms defined by the IEEE 754 standard to ensure accuracy and precision. The operations consider the sign, exponent, and significand to perform the arithmetic calculations while adhering to rounding rules and handling special cases such as NaN (Not a Number) and infinity. For example, let's perform the addition operation on two IEEE 754 single precision floating-point numbers:
  3. Convert the numbers to binary representation in the IEEE 754 format.
  4. Align the numbers based on the exponents and perform the addition of the significands.
  5. Adjust the result if necessary by normalizing the significand and updating the exponent.
  6. Check for overflow, underflow, or any special cases as defined by the IEEE 754 standard.
  7. Round the result based on the rounding mode specified (e.g., round to nearest, round towards zero, etc.). Q8. Evaluate the following by using restoration division : Divisor is 11 and Divided is 1000? Ans:-To evaluate the division using the Restoring Division algorithm, follow these steps:
  8. Set the Divisor (D) to 11 and the Dividend (A) to 1000 (the number being divided).

Ans;- In computer architecture, arithmetic overflow occurs when the result of an arithmetic operation exceeds the range that can be represented by a given data type. Let's consider an example in assembly language: Suppose we have an 8-bit signed integer data type, which can represent values from -128 to 127. If we try to add two numbers that result in a value outside this range, an arithmetic overflow will occur. Let's say we have the following values: A = 100 ; decimal value B = 50 ; decimal value In binary representation, A is 01100100 and B is 00110010. If we add A and B using an 8-bit signed integer representation, the result would be

  1. However, in two's complement representation, this binary value represents -26, not 150. Since the result (-26) is outside the range of the 8-bit signed integer data type, an arithmetic overflow has occurred. Arithmetic overflow can lead to unexpected behavior or errors in programs if not handled properly. It is important to check for and handle such cases to ensure accurate and reliable computations. Q10. Explain Booth Alogrithm and Multiply (-13) * (-11) using it. Ans:- The Booth's algorithm is a multiplication algorithm used to multiply signed numbers in binary representation. It is a more efficient method compared to traditional multiplication algorithms as it reduces the number of required additions. To multiply two signed numbers using the Booth's algorithm, the following steps can be followed:
  2. Convert the numbers to their binary representation. In this case, (-13) is represented as 1111 0011 and (-11) is represented as 1111 0101.
  3. Create a product register that is twice the bit length of the original numbers. In this case, since we have 8-bit numbers, the product register will be 16 bits.
  4. Initialize the product register with the multiplicand (in this case, (-13)) on the right half and set the left half to zero. The product register initially becomes 0000 0000 1111 0011.
  5. Next, add the negation of the multiplicand (in this case, -(-13) = 13) to the left half of the product register. The product register becomes 1111 1111 1111
  6. Initialize a multiplier bit, which is initially set to zero.
  1. Repeat the following steps for the bit length of the multiplier (in this case, 8 bits): - Check the two rightmost bits of the product register. If they are 01 or 10, perform a subtraction by adding the multiplicand (in this case, (-13)) to the product register. - If the two rightmost bits are 00 or 11, no action is needed. - Perform an arithmetic right shift on the product register, including the multiplier bit. This propagates the sign bit to the left. The rightmost bit of the product register becomes the new multiplier bit, and the leftmost bit is duplicated to maintain the sign. After completing the 8 iterations, the final product register will hold the result of the multiplication. In this case, the product register becomes 1111 0011 0000 1011, which represents the decimal value -143. Q11. Explain the addition and subtraction of two fixed point signed magnitude data with Flow chart? Ans;-

series of logic gates to generate lookahead carry signals, allowing for parallel computation of carry bits. This reduces the overall delay and improves the speed of addition.

  • Carry-Select Adders: Carry-select adders further enhance the speed of addition by using a multiplexer-based structure. They divide the input bits into groups and compute multiple carry chains in parallel. A final multiplexer selects the appropriate sum based on the computed carries. This approach reduces the critical path delay and improves the overall performance. Fast adders are essential in modern computing systems where high-speed arithmetic operations are required. By optimizing carry propagation and reducing delays, they enable faster and more efficient addition of binary numbers.
  1. Bit Pair Recoding of Multipliers: Bit pair recoding is a technique used to optimize the multiplication process in binary multiplication algorithms, such as Booth's algorithm. It involves recoding the multiplier by replacing consecutive pairs of bits with a new representation, reducing the number of partial products generated during multiplication. In binary multiplication, a partial product is generated for each bit of the multiplier. Bit pair recoding aims to minimize the number of partial products required, leading to a more efficient multiplication process. Here's how it works:
  • In bit pair recoding, two consecutive bits of the multiplier are examined at a time. If the two bits are the same (00 or 11), no action is taken. If the two bits are different (01 or 10), they are replaced with specific bit patterns.
  • The recoding patterns depend on the specific recoding scheme being used. One common recoding scheme is the Booth encoding, which replaces 01 with 11 and 10 with 01.
  • By recoding the multiplier, the number of partial products is reduced. This reduction leads to fewer additions required in the multiplication process, resulting in improved performance and efficiency. Bit pair recoding is especially useful in multiplication algorithms that involve multiple partial product additions, as it reduces the overall computation time and complexity. It is commonly employed in digital signal processing applications and in hardware implementations of multipliers, where speed and efficiency are critical factors. Q13. Define Fixed point ans floating point numbers?

Ans;-Fixed-point numbers and floating-point numbers are both representations of real numbers in computing systems, but they differ in how they store and represent the fractional part of a number. Fixed-Point Numbers: Fixed-point numbers are a way to represent real numbers with a fixed number of digits for the integer and fractional parts. The position of the decimal point is fixed and does not change. The range and precision of fixed-point numbers are determined by the number of bits allocated for the integer and fractional parts. For example, consider a fixed-point number representation with 8 bits, where 4 bits are allocated for the integer part and 4 bits for the fractional part. In this case, the range of the fixed-point number would be limited to a specific range (e.g., -8 to

  1. and the precision would be determined by the number of fractional bits (e.g., 1/16 or 0.0625). Fixed-point numbers are commonly used in applications where exact precision is not critical, or where integer arithmetic operations are sufficient. They are also computationally efficient compared to floating-point numbers since they can be processed using integer arithmetic operations. Floating-Point Numbers: Floating-point numbers represent real numbers by using a combination of a sign bit, an exponent, and a mantissa (or significand). The position of the decimal point (or binary point) can "float" based on the exponent value, enabling a wider range of representable numbers compared to fixed-point numbers. Floating-point numbers are typically represented using a standardized format, such as the IEEE 754 standard, which defines single-precision (32-bit) and double- precision (64-bit) formats. These formats allocate bits for the sign, exponent, and mantissa, allowing for a wide range of values and varying levels of precision. Floating-point numbers are well-suited for applications that require a wide range of numbers or high precision, such as scientific calculations, graphics rendering, and financial modeling. However, they introduce some limitations due to the inherent trade-offs between range, precision, and computational complexity. Q14. Define guard bits? Ans;- Guard bits, also known as guard digits, are additional bits used in floating- point representation to enhance the precision of numerical calculations. They are typically placed on the left or right side of the significand (mantissa) and serve to reduce rounding errors during arithmetic operations. When performing arithmetic operations on floating-point numbers, rounding errors can occur due to the limited precision of the significand. Guard bits help mitigate these errors by extending the precision of the operands.
  • The final result is the quotient obtained after all iterations, and the remainder is the value left in the numerator. The restoring method requires multiple iterations and can be time-consuming for large dividend and divisor values. However, it guarantees that the final result will have the correct sign and provides an exact quotient. Non-Restoring Method: The non-restoring method is an optimization of the restoring method and reduces the number of iterations needed to find the quotient and remainder. Here's how it works:
  • Similar to the restoring method, the dividend is placed in the numerator, and the divisor is placed in the denominator, and the sign of the quotient is determined.
  • A counter is set to the bit length of the dividend.
  • The algorithm begins by comparing the numerator with the denominator:
  • If the numerator is greater than or equal to the denominator, a subtraction is performed, and the result is stored as the partial quotient.
  • If the numerator is smaller than the denominator, a non-subtraction is performed, and the result is stored as the partial quotient (which is one less than the quotient).
  • The counter is decremented.
  • Steps 3 to 5 are repeated until the counter reaches zero.
  • The final result is the quotient obtained after all iterations, and the remainder is the value left in the numerator. The non-restoring method reduces the number of subtractions compared to the restoring method by performing fewer subtractions in cases where the numerator is smaller than the denominator. However, it requires an additional adjustment to obtain the correct quotient. Both the restoring method and the non-restoring method are used for integer division, with the non-restoring method providing a slight optimization in terms of the number of subtractions required. The choice of method depends on the specific requirements and constraints of the application. Q16. Give functional block diagram of sequential ALU and also explain its working? Ans:-A sequential Arithmetic Logic Unit (ALU) is a component in a computer processor that performs arithmetic and logical operations. It operates in a

sequential manner, meaning that the operations are executed one after another based on control signals and the current state of the ALU. Here is a functional block diagram of a sequential ALU: The sequential ALU consists of the following main components:

  1. Register File: The register file is a collection of registers that store the operands and results of operations. It typically includes multiple general-purpose registers, such as Accumulator, B register, and Result register. The register file holds the input data for the ALU and stores the output data after the operations are performed.
  2. ALU Control Unit: The ALU Control Unit generates control signals that determine the operation to be performed by the ALU. It takes inputs from the instruction decoder and decides which arithmetic or logical operation needs to be executed based on the instruction opcode and other control inputs. The ALU control signals are sent to the ALU to perform the specified operation.
  3. ALU: The Arithmetic Logic Unit (ALU) is the core component of the sequential ALU. It performs arithmetic and logical operations on the input data provided by the register file. The ALU can perform operations such as addition, subtraction, logical AND, logical OR, bitwise shifting, and more. It takes the inputs from the register file and the control signals from the ALU control unit to execute the desired operation.
  4. Status Flags: