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COMPUTER ORGANIZATION AND ARCHITECTURE
TIME-3 hrs 2020-Q.P
Max Marks: 80
PART-A
I. Answer any Ten of the following. Each Carries 2 marks. a) Define software. List its Types.
Ans: Software is a set of programs, which is designed to perform a well-defined function.
Types: System Software, Application Software
b) Define processor clock and clock rate.
Ans: Processor Clock: Processor circuits are controlled by a timing signal called clock. The clock designer the regular time intervals called clock cycles.
Clock rate: it means the number of pulses generated by CPU in one second.
c) Expand IEEE and ISR
Ans: The Institute of Electrical and Electronics Engineers (IEEE). Interrupt Service Routine(ISR).
d) What is addressing modes? List its types. Ans: The different ways in which the location of an operand is specified in an instruction are referred to as addressing modes. Types: Immediate mode Register mode Absolute mode Indirect mode Index mode Base with Index Base with Index and Offset Relative mode Auto increment mode Auto decrement mode
e) Define byte addressability. Ans: A computer in which each byte stored can be addressed individually is called byte addressability. It refers to hardware architectures which supports accessing individual bytes. Ex: the Intel 8008 addresses eight bits.
f) Define a Bus. Write its usage. Ans: A group of lines that serve as connecting path for several devices is called a bus. Usage: to transfer data and other information between devices.
g) What is an Interrupt hardware? Ans: It is an interrupt generated from an external device or hardware. In a hardware interrupt, all the devices are connected to the Interrupt Request Line. A single request line is used for all the n devices.
h) Mention four functions of Single bus organization. The internal bus carries data within the motherboard. External buses carry data to peripherals and other devices attached to the motherboard. Data bus: carry data from input device Address bus: the processor uses address bus to send address of memory. Control bus: A set of individual signal carrying information at different instance of time.
i) What is memory-mapped I/0. Ans: A method to perform input/output(I/O) operations between the central processing unit and peripheral devices in a computer that uses one address space for memory and IO devices.
j) What is the use of Cache memory. Ans: It is an extremely fast memory type that acts as a buffer between RAM and the CPU It is used to reduce the average time to access data from the main memory.
k) Write a record table of Booth’s algorithm. Ans: MULTIPLIER VERSION OF MULTIPLIED SELECTED BY BIT 1 0 0 0 0 * M 0 1 +1 +1M 1 0 -1 -1M 1 1 0 0*M
l) Define DMA. Ans: DMA controller is a hardware unit that allows I/O devices to access memory directly without the participation of the processor.
II. Answer any six questions. Each carries 5 marks.
- Explain basic operational concepts of a processor with a diagram.
If the instruction involves an operation by the ALU, it is necessary to obtain the required operands. An operand in the memory is fetched by sending its address to MAR & Initiating a read cycle. When the operand has been read from the memory to the MDR, it is transferred from MDR to the ALU. After one or two such repeated cycles, the ALU can perform the desired operation. If the result of this operation is to be stored in the memory, the result is sent to MDR. Address of location where the result is stored is sent to MAR & a write cycle is initiated. The contents of PC are incremented so that PC points to the next instruction that is to be executed.
- Explain Multiple Bus organization with example.
Ans:
- All general-purpose registers are combined into a single block called the register file.
- Register-file has 3 ports. There are 2 outputs allowing the contents of 2 different registers to be simultaneously placed on the buses A and B.
- Register-file has 3 ports.
- Two output-ports allow the contents of 2 different registers to be simultaneously placed on buses A & B.
- Third input-port allows data on bus C to be loaded into a third register during the same clock-cycle.
- Buses A and B are used to transfer source-operands to A & B inputs of ALU.
- Result is transferred to destination over bus C.
- Increment-unit is used to increment PC by 4.
- Control sequence for the instruction Add R4,R5,R6 is as follows
PCout, R=B, MARin, Read, IncPC
WMFC
MDRout, R=B, IRin
R4outA, R5outB, SelectA, Add, R6in, End
- Instruction execution proceeds as follows: Step 1--> Contents of PC are passed through ALU using R=B control-signal and loaded into MAR to start a memory Read operation. At the same time, PC is incremented by 4. Step2--> Processor waits for MFC signal from memory. Step3--> Processor loads requested-data into MDR, and then transfers them to IR. Step4--> The instruction is decoded and add operation take place in a single step.
- Explain different instruction types with examples.
Ans: The operation of adding two numbers is a fundamental capability in any computer. The statement C = A + B To carry out this action, the contents of memory locations A and B are fetched from the memory and transferred into the processor where their sum is computed. This result is then sent back to the memory and stored in location C.
The basic instruction involves three steps:
- Three address machine instruction.
- Two address machine instruction
- One address machine instruction 01. Three address machine instruction: This three-address instruction can be represented symbolically as Add A, B, C
- Operands A and B are called the source operands, C is called the destination operand, and Add is the operation to be performed on the operands. A general instruction of this type has the format.
Operation Source1, Source 2, Destination
02. Two address machine instruction Two- address instructions of the form Operation Source, Destination are available.
- An Add instruction of this type is Add A, B Which performs the operation B ← [A] + [B]. Here the contents of locations A and B, without destroying either of them, and to place the sum in location C. The problem can be solved by using another two-address instruction that copies the contents of one memory location into another. Such an instruction is Move B, C Which performs the operations C ← [B], leaving the contents of location B unchanged.
06. Explain Interrupt hardware with diagram. Ans: An I/O device requests an interrupt by activating a bus line called interrupt-request. ⚫ Most computers are likely to have several I/O devices that can request an interrupt.
⚫ A single interrupt-request line may be used to serve n devices as depicted in Figure 4.6.
⚫ All devices are connected to the line via switches to ground.
To request an interrupt, a device closes its associated switch.
⚫ Thus, if all interrupt-request signals INTR1 to INTRn are inactive, that is, if all switches are open, the voltage on the interrupt-request line will be equal to 𝑉𝑉𝑉𝑉𝑉𝑉.
⚫ This is the inactive state of the line.
⚫ When a device requests an interrupt by closing its switch, the voltage on the line drops to 0, causing the interrupt-request signal, INTR, received by the processor to go to 1. Since the closing of one or more switches will cause the line voltage to drop to 0, the value of INTR is the logical OR of the requests from individual devices, that is, INTR = INTR1 + INTR2 + ⋯ + INTRn
⚫ It is customary to use the complemented form, INTR, to name the interrupt-request signal on the common line, because this signal is active when in the low-voltage state. ⚫ In the electronic implementation of the circuit in Figure 4.6, special gates known as open-collector (for bipolar circuits) or open-drain (for MOS circuits) are used to drive the INTR line. ⚫ The output of an open-collector or an open-drain gate is equivalent to a switch to ground that is open when the gate's input is in the 0 state and closed when it is in the 1 state. ⚫ The voltage level, hence the logic state, at the output of the gate is determined by the data applied to all the gates connected to the bus. ⚫ Resistor R is called a pull-up resistor because it pulls the line voltage up to the high- voltage state when the switches are open.
- Explain DMA controller with diagram.
Ans: DMA controller is a control circuit that performs DMA transfer, is a part of the I/O device interface. It performs functions that normally be carried out by the processor. DMA controller must increment the memory address and keep track of the number of transfers. The operations of DMA controller must be under the control of a program executed by the processor. To initiate the transfer of block of words, the processor sends the starting address, the number of words in the block and the direction of the transfer. On receiving this information, DMA controller transfer the entire block and informs the processor by raising an interrupt signal. While a DMA transfer is taking place, the processor can be used to execute another program. After the DMA transfer is completed, the processor can return to the program that requested the transfer. Three registers in a DMA interface are: Starting address Word count Status and control flag
08. How addition and Subtraction Carried out using circle notation with two Examples.
Ans: ex:
Implementation of Variable and Constants
The value can be changed as needed using the appropriate instructions. They are two accessing needs to access the variables. They are:
Register mode Absolute mode
Register mode
- The operand is the contents of a processor register; the name (address) of the register is given in the instruction.
Absolute mode
- The operand is in a memory location; the address of this location is given explicitly in the instruction. (In some assembly languages, this mode is called Direct).
The instruction Move LOC, R
- Processor registers are used as temporary storage locations where the data is a register are accessed using the Register mode.
- The Absolute mode can represent global variables in a program.
- A declaration such as
Integer A, B;
Immediate mode
- The operand is given explicitly in the instruction.
For example, the instruction Move 200immediate, R
- Places the value 200 in register R0. Clearly, the Immediate mode is only used to specify the value of a source operand. Using a subscript to denote the Immediate mode is not appropriate in assembly languages.
- A common convention is to use the sharp sign (#) in front of the value to indicate that this value is to be used as an immediate operand. Hence, we write the instruction above in the form
- Move #200, R
Indirect mode
- The effective address of the operand is the contents of a register or memory location whose address appears in the instruction.
MOVE [R1],RO
Base with Index: Here, the EA is calculated by adding the base register content with index register. Base with index and offset: Here, the address of operand is calculated by adding the content of the base value ,index register value and offset value.
Additional mode:
Auto increment mode The effective address of the operand is the contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically to point to the next item in a list. (Ri)+ Auto decrement mode The contents of a register specified in the instruction are first automatically decremented and are then used as the effective address of the operand.
- a) Explain register transfer gating with diagram.
Ans:
MAR - [R1]
- Begin Read operation on the memory bus
- Wait for the response of the MFC from the memory
- Load MDR from the memory bus
- R2 - [MDR]
Signals activated for that problem are:
- WMFC MDRout
- R1out, MARin,
- Read MDRinE, , R2in 12. Explain hardwired control and micro-programmed control unit with a diagram.
Ans: • To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence.
- Computer designers use a wide variety of techniques to solve this problem.
- The approaches used fall into one of two categories: hardwired control and microprogrammed control.
- The required control signals are determined by the following information
- Contents of the control step counter
- Contents of the instruction register
- Contents of the condition code flags
- External input signals, such as MFC and interrupt requests
The addresses of the memory locations are symbolically given as NUM1, NUM2, ……, NUMn and a separate Add instruction is used to add each number to the contents of register R1. After all the numbers have been added, the result is placed in memory location SUM.
- Writing separate Add instruction to perform addition is not only tedious but also requires more memory space to store the instruction. So, instead of using separate Add instructions to add the numbers, we can use a single Add instruction inside a program loop as shown in below figure.
The sequence of instruction inside the loop are executed as many times as needed During each pass , the address of the next number in the list is determined , the data at that location is fetched and then added to register R1.
- Let ‘n’ (the number of entries in the list) be stored in memory location N. Register R0 is used as a counter to check how many times the loop should be executed. Therefore, R0 contains the contents of location NUM, i.e., value ‘n’ .Within the body of the loop, the instruction.
- Decrement R0 decreases the contents of R0 by 1 for every pass through the loop. Execution of the loop is repeated if R0 is greater than zero.
- There is a special instruction Branch>0 LOOP in the program. This type of instruction loads a new value into the PC. Now, the processor fetches and executes the instruction at this new address called Branch target instead of going to the next instruction sequentially. The program control can be changed conditionally or unconditionally, A conditional branch instruction causes a branch only if the specified condition is satisfied. If not, the PC is incremented to fetch the next instruction in sequence.
- The instruction Branch>0 LOOP is a conditional branch instruction that causes a branch to location LOOP if the result of the immediately preceding instruction (Decrement R0) is greater than zero. That is, the loop is repeated if there are data in the list to be added to R1. At the end of nth pass, decrement instruction produces a value zero. Now, the condition fails and branching will not occur. So, the next Move instruction is executed and the addition result in R1 is moved to memory location SUM. 14. a) Explain Memory mapped and I/0 mapped.
b) Explain daisy chain with diagram
Ans: NOT IN syllabus. (not necessary)
Write operation: It stores a new value in memory.
09. Define INTR and INTA signals. Ans: INTA is a signal used to identify that a CPU has an interrupt made by the interrupt controller. Short form International Trademark Association, INTA is an international organization actively pursuing public policy matters. Computer acronyms, Hardware terms, INTR (Interrupt). 10. Define interrupts. Ans: Interrupt is the mechanism by which modules like I/O or memory may interrupt the normal processing by CPU. It may be either clicking a mouse, dragging a cursor, printing a document etc the case where interrupt is getting generated. 11. Mention any four assembler directives. Ans: Initialize memory Assemble conditional blocks Define global variables Assemble code and data into specified sections Reserve space in memory for uninitialized variables. 12. Define fast adders. Ans: A carry-lookahead adder (CLA) or fast adder is a type of electronics adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits.
ii. Answer any 6 of the following.
13. Explain basic operational concepts of a processor with a diagram. Ans:
The fig shows how memory & the processor can be connected.
In addition to the ALU & the control circuitry, the processor contains a number of registers used for several different purposes. The instruction registers (IR) Holds the instructions that is currently being executed. Its output is available for the control circuits which generates the timing signals that control the various processing elements in one execution of instruction. The program counter PC This is another specialized register that keeps track of execution of a program. It contains the memory address of the next instruction to be fetched and executed. Besides IR and PC, there are n-general purpose registers R0 through Rn-1. The other two registers which facilitate communication with memory are
- MAR (Memory Address Register) • It holds the address of the location to be accessed.
- MDR(Memory Data Register) • It contains the data to be written into or read out of the address location. Operating Steps are:
Programs reside in the memory & usually get these through the I/P unit. Execution of the program starts when the PC is set to point at the first instruction of the program. Contents of PC are transferred to MAR and a Read Control Signal is sent to the memory. After the time required to access the memory elapses, the address word is read out of the memory and loaded into the MDR. Now contents of MDR are transferred to the IR & now the instruction is ready to be decoded and executed. If the instruction involves an operation by the ALU, it is necessary to obtain the required operands. An operand in the memory is fetched by sending its address to MAR & Initiating a read cycle. When the operand has been read from the memory to the MDR, it is transferred from MDR to the ALU. After one or two such repeated cycles, the ALU can perform the desired operation. If the result of this operation is to be stored in the memory, the result is sent to MDR. Address of location where the result is stored is sent to MAR & a write cycle is initiated. The contents of PC are incremented so that PC points to the next instruction that is to be executed.
14. Explain two types of byte addressability. Ans: There are two ways that byte addresses can be assigned across words, as shown in below figure.
