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The solution to quiz 3, which involves analyzing the active control bits and memory operations in a single bus architecture. The solution includes the actions taken in each clock cycle, the values of the register contents, and the identification of the data memory location and its contents after clock no. 19.
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Quiz 3 – solution The table given below lists the ACTIVE CONTROL BITS observed in the clock cycles excluding the FETCH cycles, when a particular program is run. (a) Using the given documentation of the Single Bus Architecture, write down the action giving numerical values of the Register contents for each of the 11 listed clock cycles. [6] (b) Find the values of the contents of the Registers R 0 and R 2 after clock no. 19. [2] (c) Identify the Data Memory location used in the program and the contents of that memory location after clock no. 19. [2] (a) The missing Clock nos. correspond to the FETCH cycles. Hence Clock nos. 2, 4, 6, 17 and 19 correspond to instructions having no READ cycle, whereas the consecutive clock nos. 8 - 9 , 11 - 12 and 14- 15 correspond to instructions having both READ and EXECUTE cycles. [6] Clock Active Control Bits Action 2 SPC, RD, LRN, IPC, SIF (
9 EOR, SAL, LRN,^ SIF^ (
12 ERN, SAL, LR 0 , SIF (
14 SPC, RD, LOR, IPC, EFL, SIF (