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Designed CMOS NOR gate in Cadence Virtuoso and anaylysed
Typology: Summaries
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Abstract The latch is a characteristic circuit (does not require a clock signal to work), and it has two stable states, HIGH (“1”) and LOW (“0”), which can be used to store binary data. Many sequential circuits and larger storage devices, such as switch registers, use latches as the main building block. The simplest latch is the Set-Reset latch (S-R). This paper carried out a comparison against CMOS SR latch using NOR designed in different logic styles in terms of power and delay. The simulation results are produced using the Cadence Tool. And using these
Key word – CMOS SR Latch, NOR, VLSI Design, Cadence
1. INTRODUCTION Circuit realization for low power and low area has become an important issue with the growth of integrated circuit towards very high integration density and high operating frequencies. The SR latch sets the output to 1, while the R input resets the output to 0. When both S and R inputs are at 1, the latch is said to be in an undefined state [1]. Cadence virtuoso [ 2 ] is a very important EDA tool for electronics students learning about IC design/analysis and PCB design/analysis. At undergraduate level, virtuoso is majorly used for custom design and analysis of circuits based on MOS technologies, especially in the CMOS VLSI course. The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitic in the IC verification flow, enabling time saving by combining package/board layout connectivity data with the IC layout parasitic electrical model. It enables engineers to design concurrently across chip, package, and board, saving time and minimizing errors. It is ideal for designs that integrate multiple heterogeneous ICs, including RF, analog, and digital devices. It is easy to simulate designs in cadence virtuoso [ 3 ] platform. The steps to simulate in the cadence tool are as follows: -
Shivali Panwar VLSI Design – 24MEC Department of Electronics and Communication Engineering NIT Hamirpur (HP)
The bistable element is able to remember or store one bit of information. However, because it does not have any inputs, we cannot change the information bit that is stored in it. In order to change the information bit, we need to add inputs to the circuit. The simplest way to add inputs is to replace the two inverters with two NOR gates as shown in Figure 1(a). This circuit is called a SR latch. In addition to the two outputs Q and Q̅, there are two inputs S and R for set and reset respectively. Following the convention, the prime in S and R denotes that these inputs are active low. The SR latch can be in one of two states: a set state when Q = 1 or a reset state when Q = 0. The NOR gate only gives “1” when both inputs are “0”, with any other input combination the output is “0”. If we see truth table that when S and R are equal to “0”, the output Q remain the same as it was. This is memory function of SR latch because it saves the previous value. Suppose the Q output is “1” in the present state. If you know place both inputs in “0”, then the output will remain “1”. To make the SR latch go to the set state, we simply assert the S input by setting it to 0. If both gates have exactly the same delay, then they will both output a 0 at exactly the same time. Feeding the zeros back to the gate input will produce a 1, again at exactly the same time, which again will produce a 0, and so on and on. This oscillating behaviour, called the critical race, will continue forever. If the two gates do not have exactly the same delay, then the situation is similar to de-asserting one input before the other, and so the latch will go into one state or the other. However, since we do not know which is the faster gate, therefore, we do not know which state the latch will go into. Thus, the latch’s next state is undefined [4]. In order to avoid this indeterministic behaviour, we must make sure that the two inputs are never de-asserted at the same time. Note that both of them can be de-asserted, but just not at the same time. In practice, this is guaranteed by not having both of them asserted. Another reason why we do not want both inputs to be asserted is that when they are both asserted, Q is equal to Q̅, but we usually want Q to be the inverse of Q̅.
3. PRINCIPLE Latch is a digital circuit which converts its output according to its inputs instantly. To implement latches, we use different logic gates. Fig.2. SR latch symbol Fig. 3. Schematic diagram Simulating and seeing the transient analysis of CMOS SR latch are as follows: - The delay calculated is 835.6E-9 ns. The average power calculated is 1.8 microwatt.