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Differential Amplifiers (Chapter 8
- Differential amplifiers are pervasive in analog electronics
- Low frequency amplifiers
- High frequency amplifiers
- Operational amplifiers – the first stage is a differential amplifier
- Analog modulators
- Logic gates
- Advantages
- Large input resistance
- High gain
- Differential input
- Good bias stability
- Excellent device parameter tracking in IC implementation
- Examples
- Bipolar 741 op-amp (mature, well-practiced, cheap)
- CMOS or BiCMOS op-amp designs (more recent, popular)
Amplifier With Bias Stabilizing Neg Feedback Resistor
- Single transistor common-emitter or common-source amplifiers often use a bias
stabilizing resistor in the common node leg (to ground) as shown below
- Such a resistor provides negative feedback to stabilize dc bias
- But, the negative feedback also reduces gain accordingly
- We can shunt the common node bias resistor with a capacitor to reduce the negative
impact on gain
- Has no effect on gain reduction at low frequencies, however
- Large bypass capacitors are difficult to implement in IC design due to large area
- Conclusion: try to avoid using feedback resistor R2 in biasing network
Differential Amplifier with Two Simultaneous Inputs
- The differential amplifier topology shown at
the left contains two inputs, two active
devices, and two loads, along with a dc
current source
- We will define the
- differential mode of the input v (^) i,dm = v 1 – v (^2)
- common mode of the input as v (^) i,cm= ½ (v 1 +v 2 )
- Using these definitions, the inputs v 1 and v (^2)
can be written as linear combinations of the
differential and common modes
- v 1 = v (^) i,cm + ½ v (^) i,dm
- v 2 = v (^) i,cm – ½ v (^) i,dm
- These definitions can also be applied to the
output voltages
- Differential mode v (^) o,dm = v (^) o1 – v (^) o
- Common mode v (^) o,cm = ½ (v (^) o1 + v (^) o2)
- Alternately, these can be written as
- v (^) o1 = v (^) o,cm + ½ v (^) o,dm
- v (^) o2 = v (^) o,cm – ½ v (^) o,dm
Bipolar Transistor Differential Amplifier
- Q1 & Q2 are matched (identical) NPN
transistors
- Rc is the load resistor
- Placed on both sides for symmetry, but could be used to obtain differential outputs
- I (^) o is the bias current
- Usually built out of NPN transistor and current mirror network
- r (^) n is the equivalent Norton output resistance of the current source transistor
- Input signal is switching around ground
- V (^) ref = 0 for this particular design
- Both sides are DC-biased at ground on the base of Q1 and Q
- vBE is the forward base-emitter voltage across
the junctions of the active devices
- Since Q1 and Q2 are assumed matched, Io
splits evenly to both sides
- I (^) C1 = I (^) C2 = Io /
Bipolar Transistor Operation (1D Device)
BJT operation:
- An external voltage (0.75-0.85 V) is applied
to forward-bias the emitter-base junction
- Electrons are injected from the emitter into
the base comprising the majority of the
emitter current
- Holes are injected from the base into the emitter, as well, but their numbers are much smaller, since N (^) D,e >> N (^) A,b
- Since X (^) B << Ln in the base, most of the
injected electrons get to the collector
without recombining with holes. Any holes
that do recombine with electrons in the base
are supplied as base current.
- Electrons reaching the collector are collected
across the base-collector depletion region.
- Since most of the injected electrons reach
the collector and only a few holes are
injected into the emitter, or recombine with
electrons in the base, I B << I C, implying that
the device has a large current gain.
- Shown at left are the effects of
different NPN bias conditions
on the energy bands and the
electron concentrations:
(a) No bias (thermal equilibrium)
- Fermi levels are flat
- Electron concentration is N (^) D in emitter and collector and n (^) i^2 /N (^) A in the base
(b) both junctions reverse biased
- Increased E-B & B-C barriers
- Increase in depletion regions
- Electron density in base = ~
(c) both junctions forward biased
- Reduced barrier heights
- Electrons injected into base from both emitter and collector
(d) forward-biased emitter, reverse-
biased collector
- Small E-B/large C-B barriers
- Electrons injected from emitter
- Electron density = ~ 0 at C-B junction and appears linear in base region (small W (^) B )
Ebers-Moll BJT DC Model Current Equations
- The Ebers-Moll model may be used under all junction bias conditions (i.e., forward-
active, inverse, saturation, and cut-off) to estimate the terminal currents.
Bipolar Transistor Collector Characteristics
- Shown below is a set of BJT (bipolar junction transistor) collector characteristics
- I (^) C versus V (^) CE with IB as the parameter
- The curves have several regions of operation
- At low V (^) CE both the emitter-base junction and the collector-base junction are forward-biased, resulting in what is called saturation in the bipolar transistor - The base volume is flooded with mobile carriers injected from both E-B and C-B junctions
- At higher (normal) V (^) CE only the emitter-base junction is forward-biased, while the collector- base junction is reverse-biased, resulting in the normal active (forward mode) region - The carrier concentration is pinned at zero (i.e. very small) at the collector junction, resulting in a linear (triangular) distribution of charge in the base - Non-zero slope in normal active region is caused by base width narrowing due to increase in V (^) CB reverse bias and corresponding increase in C-B depletion region ( Early Effect named after Jim Early)
- At even higher V (^) CE the transistor enters the onset of avalanche breakdown at the CB junction
The non-zero slope in the forward mode region is modeled, as shown below, with a linear term V (^) CE /VA , where VA is the Early Voltage.
Definitions of fT and fmax
- Cuttoff frequency f (^) T can be defined as a series of time constants including base storage
time τb, emitter storage time τe , collector storage time τc , and several RC time constants
due to emitter and collector depletion capacitances and collector-to-substrate capacitance
IBM SiGe Design Kit Training: Technology, IBMMicroelectronics, Burlington, VT, July 2002
terms in order of
significance are the
base storage time τb,
emitter storage time τe ,
and the depletion
charge terms
(kT/qIc)(Cje + Cjc)
technology the last
several terms are
usually negligible since
Re, Rc, and R ns are
small
SiGe NPN Bipolar β and fT versus Current
- Plotted at left are the current gain β and f (^) T
versus collector current for two different
emitter width NPN transistors
- Both β and fT drop off at high current density due to base push-out (called the Kirk Effect ) - When the number of injected electrons exceeds the N type doping of the collector region, the base-collector space charge region pushes all the way to the heavily-doped N+ subcollector. - The use of a self-aligned collector pedestal N implant raises the doping in the intrinsic portion of the collector N epi and prevents base push-out until very high current (<1 mA/um2) - Use of a self-aligned pedestal implant limits the increase in Ccb due to the higher collector doping (which is only in the intrinsic portion of the device)
- The two curves in the plots are shifted by the area of the emitter. - Using minimum width for the emitter improves base resistance and therefore improves device performance.
Harame, et al., IEEE Trans ED,Vol. 48, No. 11, Nov. 2001
BJT SPICE Model Parameters
- Typical SPICE circuit model parameters for a vintage 1 um silicon bipolar technology are
given below (from Johns and Martin, Analog Integrated Circuit Design , 1997, p. 65)
- The f (^) T would be about 13 GHz, based on the forward base transit time τF of 12 ps
- Reverse current gain-bandwidth product would be about 40 MHz based on τR of 4 ns
- Rb of 500 ohms and C (^) cb of 18 fF suggest a relatively low f (^) max of about 7-8 GHz f (^) max = [f (^) T / 8 π RbCcb] ½
Small-Signal Model Analysis for Single Input Diff Amp
- Consider transistor Q2 with grounded base
- dc small-signal model shown in top-left figure
- Use the test voltage approach to calculate Q2’s input impedance looking into emitter
- Using KCL equations, we can write itest = v (^) test/rπ – βoib2 where ib2 = - v (^) test/rπ
- Rearranging and solving for v (^) test/itest, we have r (^) th2 = v (^) test/itest = r π /( β o + 1) = ~ r π / β o = 1/g (^) m
- Generally g (^) m2 is large, causing rth2 to act like an ac short
- Consider transistor Q1 with Q2 replaced by r (^) th
- Since r (^) th2 is much smaller than r (^) n (output impedance of Io), we will neglect rn
- Writing KCL, we have v (^) in = ib1 rπ 1 + i (^) b1 (βo + 1) r (^) th2 = i (^) b12 rπ 1
- where we assumed rπ 1 = rπ 2
- We can now find vout as a function of vin v (^) out = - ic1Rc = - βoib Rc = - βov (^) in Rc/2rπ 1 = - ½ g (^) mRcv (^) in
- where we have used g (^) m = βo/rπ 1
- Small signal gain A (^) v = vout /vin = - ½ gm R (^) c
Bipolar Diff Amp with Differential Inputs (continued)
- Solving for the output voltages we can obtain
- v (^) o1 = -ic1RC = - βoib1RC = - (βo /rπ)v (^) a(t)R (^) C and v 02 = + (βo /rπ)v (^) a(t)R (^) C
- We can now find the gain with differential-mode input and single-ended output or with
differential-mode input and differential output
A (^) dm-se1 = v 01 /v (^) idm = -g (^) mR (^) C /2 and A (^) dm-se2 = + g (^) mR (^) C / A (^) dm-diff = (v 01 – v 02 )/ v (^) idm = - g (^) mR (^) C
- Since corresponding currents on the left and right side of the differential small-signal
model are always equal and opposite, implying that no current ever flows throw r n
- Node E acts as a “ virtual ground ”
- If the output resistances of Q1 and Q2 are low enough to require keeping them in the
analysis, we simply replace R C with the parallel combination of RC||r o for transistor Q
and Q
Small-Signal Model of BJT Diff Amp with CM Inputs
- The figure below is the small-signal model for the diff amp with common-mode inputs
- v1 = v2 = v (^) b(t) and v (^) icm = ½ (v1 + v2) = v (^) b(t)
- The common-mode currents from both inputs flow through rn as shown by the two loops
- in = 2(βo + 1) i (^) b1 = 2 (βo + 1) i (^) b
- and therefore, v (^) b = i (^) brπ + 2(βo+ 1)i (^) br (^) n or ib = v (^) b/[rπ + 2(βo+ 1)r (^) n ]
- The collector voltages can be found as
- v 01 = v 02 = - βoRC v (^) b/[rπ + 2(βo+ 1)r (^) n ] = ~ - g (^) mRC v (^) b/ [1 + 2g (^) mr (^) n]
- The common-mode gain with single-ended output is given by
- A (^) cm-se1 = A (^) cm-se2 = v (^) o1/v (^) icm = v (^) o2 /v (^) icm = - g (^) mR (^) C /[1 + 2g (^) mr (^) n ] = ~ -R (^) C /2r (^) n
- The common-mode gain with differential output is A (^) cm-diff = (v (^) o1 – vo2)/vicm = 0
- Do Example 8.1, p. 488
