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- Implementing Logic in CMOS 1
3. Implementing Logic in CMOS
Jacob Abraham
Department of Electrical and Computer Engineering
The University of Texas at Austin
VLSI Design
Fall 2020
September 3, 2020
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 1 / 37
Static CMOS Circuits
N- and P-channel Networks N- and P-channel networks implement logic functions Each network connected between Output and VDD or VSS Function defines path between the terminals
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 1 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 2
Duality in CMOS Networks
Straightforward way of constructing static CMOS circuits is to implement dual N- and P- networks N- and P- networks must implement complementary functions Duality sufficient for correct operation (but not necessary)
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 2 / 37
Constructing Complex Gates
Example: F = (A · B) + (C · D) (^1) Take uninverted function F = (A · B) + (C · D) and derive N-network (^2) Identify AN D, OR components: F is OR of AB, CD (^3) Make connections of transistors
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 3 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 4
Example of Compound Gate
F = (A + B + C) · D)
Note: N- and P- graphs are duals of each other In this case, the function is the complement of the switching function between F and GND
Question: Does it make any difference to the function if the transistor with input D is connected between the parallel A, B, C, transistors and GND? What about the electrical behavior? ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 6 / 37
Example of More Complex Gate
OU T = (A + B) · (C + D) · (E + F + (G · H))
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 7 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 5
Example of More Complex Gate
OU T = (A + B) · (C + D) · (E + F + (G · H))
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 7 / 37
Exclusive-NOR Gate in CMOS
Note: designs such as these should be checked very carefully for correct behavior using circuit simulation
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 8 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 7
Example of Another Complex CMOS Gate
This circuit does not have a pMOS network – just one transistor for each function; it will work only if F and G are complements of each other. Why?
Can evaluate the voltages at F and G ({0,VDD}) for each value of x, y, and z
F = x·y·z+x·y·z+x·y·z+x·y·z
G = x·y·z+x·y·z+x·y·z+x·y·z
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 11 / 37
Example of Another Complex CMOS Gate
This circuit does not have a pMOS network – just one transistor for each function; it will work only if F and G are complements of each other. Why?
Can evaluate the voltages at F and G ({0,VDD}) for each value of x, y, and z
F = x·y·z+x·y·z+x·y·z+x·y·z
G = x·y·z+x·y·z+x·y·z+x·y·z
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 11 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 8
Example of Another Complex CMOS Gate, Cont’d
Can also follow every path from F and G to GND and identify values of x, y, and z which will enable the path to be enabled.
F = x · y + x · y · z + x · y · z F = (x + y) · (x + y + z) · (x + y + z) = (y + x · z) · (x + y + z) = x · y + y · z + x · z
G = x · y · z + x · y · z + x · y = x · y + x · z + y · z
Can you describe the functions in simple terms? (Hint: look at the number of input variables which are true (or false) when the output is 1.) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 12 / 37
Example of Another Complex CMOS Gate, Cont’d
Can also follow every path from F and G to GND and identify values of x, y, and z which will enable the path to be enabled.
F = x · y + x · y · z + x · y · z F = (x + y) · (x + y + z) · (x + y + z) = (y + x · z) · (x + y + z) = x · y + y · z + x · z
G = x · y · z + x · y · z + x · y = x · y + x · z + y · z
Can you describe the functions in simple terms? (Hint: look at the number of input variables which are true (or false) when the output is 1.) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 12 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 10
Pass Transistors and Transmission Gates
Transistors can be used as switches; however, they could produce degraded outputs
Transmission gates pass both 0 and 1 well
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 14 / 37
Pass Transistor Logic
“Pull-Up” Circuit Used to restore degraded logic 1 from output of nMOS pass transistor
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 15 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 11
Pass Transistor Logic – Better Layout
Group similar transistors, so they can be in the same well
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 16 / 37
Tristates
Tristate Buffer produces Z (high impedance) when not enabled EN A Y 0 0 Z 0 1 Z 1 0 0 1 1 1
Non-Restoring Tristate Transmission gate acts as a tristate buffer Only two transistors, but nonrestoring Noise on A is passed to Y
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 17 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 13
Transmission Gate MUX
Nonrestoring MUX Uses two transmission gates =⇒ only 4 transistors
Inverting MUX – adds an inverter Uses compound gate AOI Alternatively, a pair of tristate inverters (same thing)
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 20 / 37
4:1 Multiplexer
A 4:1 MUX chooses one of 4 inputs using two selects Two levels of 2:1 MUXes Alternatively, four tristates
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 21 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 14
D Latch
Basic Memory Element When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a., transparent latch or level-sensitive latch
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 22 / 37
D Latch, Cont’d
D Latch Design: MUX chooses between D and old Q
D Latch Operation
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 23 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 16
Race Condition – Hold Time Failure
Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 26 / 37
Non-Overlapping Clocks
A simple way to prevent races This works as long as non-overlap exceeds clock skew Used in safe (conservative) designs Industry does not generally use this approach – managing skew more carefully instead
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 27 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 17
Gate Layout
Building a library of standard cells Layout can be time consuming One solution is to have layouts of commonly used functions (Inverter, NAND, OR, MUX, etc.), designed to fit together very well
Standard cell design methodology VDD and GN D should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts One of the large industry suppliers is ARM, others include TSMC and other foundries
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 28 / 37
Examples of Standard Cell Layout
Inverter
NAND
Horizontal N-diffusion and P-diffusion strips Vertical Polysilicon gates Metal1 VDD rail at top, Metal1 GN D rail at bottom 32 λ by 40λ ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 29 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
- Implementing Logic in CMOS 19
Example Circuit 1
Fill in the Karnaugh map to represent the Boolean function implemented by the pass-transistor circuit.
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 32 / 37
Example Circuit 1
F(a,b,c,d,e):
a
b
c
d
e e
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 33 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
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Example Circuit 2
Find the function, F, implemented by the following circuit
A + BC + B C
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 34 / 37
Example Circuit 2
Find the function, F, implemented by the following circuit
A + BC + B C
ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, September 3, 2020 34 / 37
Department of Electrical and Computer Engineering, The University of Texas at Austin
