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REALIZATION OF STATE MACHINE
A sequential circuit is also known as an Algorithmic State Machine(ASM) or simply a State Machine. These names are often used when the sequential circuit issued to control a digital system that carries out a step-by-step procedure or algorithm. The stategraphs are used to define state machines for controlling digital circuits like adders, multipliers,and dividers. As an alternative to using state graphs, a special type of flowchart, called a StateMachine flowchart or SM Chart, is also widely used to describe the behavior of a state machine.Flowcharts are useful in software design, similarly SM Charts are useful in thehardware design of digital systems. This is also special type of a flow chart state machineflowchart, or SM chart for short. SM charts are also called ASM (algorithmic state machine)charts. These SM Charts have many advantages. It is often easier to understand the operation of adigital system by inspection of the SM chart instead of the equivalent state graph. A given SMchart can be converted into several equivalent forms, and each form leads directly to a hardwarerealization.
SM Charts
A State Machine chart which is similar to a flow-chart is used to describe the behavior of a digital system or state machine.State Machine charts are also known as AlgorithmicState Machine(ASM) Chart. The ASM chart has many advantages over state graphs.It is also easy to understand the operation of a digital system by the inspection of the SM Chartrather than the state graph.The basic difference between an ordinary flow chart and SM chart is that ,certain specific rulesmust be followed to constructing the SM chart ,but no such specific rules are to be followed inthe case of flow-chart. A State Machine Chart can be constructed from the State Graph of a Digital system.There are three important components in an SM Chart. They are (i)State Box (ii) Decision Boxand (iii) Conditional output Box
State Box
The state box contains a state name followed by a slash(/) and an optional outputlist. After the state assignment ,a state code must be placed outside the box at the top.
Decision Box
A decision box is represented by the diamond shape symbol with true and False branches. The condition placed in the box is a Boolean expression that is evaluated to determinewhich branch is true.
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Conditional output Box
The conditional output box , which has curved ends contains a conditional output list. The conditional outputs depend on both the state of the system and inputs.
Fig 5.1 SM Chart Component
Specific Rules for constructing SM Chart
Certain rules must be followed while constructing an SM block. For every valid combination ofinput variables ,there must be exactly one exit path defined .This is necessary because ,eachallowable input combination must lead to a single next state.The second rule is no internal feedback within an SM block is allowed. This is shown in the diagram below.
Fig 5.1 SM Block
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Realization of SM Charts :
The realization of SM charts is done using similar methods used to realize state graphs. Therealization consists of a combinational sub network ,together with flip-flops for storing the statesof the network. Sometimes it is possible to identify equivalent states in an SM chart andeliminate redundant states. However, in an SM chart all inputs are not tested in every state, makes the reduction procedure more difficult. Even if the number of states in a SMchart can be reduced, it is not always desirable to do so because combining states may make theSM chart more difficult to interpret. Before deriving next-state and output equations from an SM chart, a state assignment must bemade. The best way of making the assignment depends on how the SM chart is realized. If gatesand flip-flops (or the equivalent PLD realization) are used, the guideline method of stateassignment is more useful.
As an example let us consider the realization of a binary counter using one PLA and two D-Flip- flops.The SM chart of the Multiplier is shown below.
Next, the multiplier whose SM chart is shown above is implemented using a PLA and two Dflip- flops connected, as shown in figure below. The PLA has five inputs and six outputs. Here binary assignment is made for states.(S0 = 00, S1 = 01,etc.). Each row in the PLA tablecorr esponds to one of the link paths in the SM chart. Because S0 has two exit paths, the table hastwo rows for present state S0. Because only Stis tested in S0, Mand K are don’t-cares asindicated by dashes.
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Fig 5.4 SM chart implementation using PLA and Flip-Flop
Xilinx 3000 series FPGAs
XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high- density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an FPGA is shown in Figure 5.5. The development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the configuration program. The FPGA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial configuration program storage in a one-time programmable package. The XC3000 Field Programmable Gate Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades.
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- XC3000A Family — The XC3000A is an enhanced version of the basic XC3000 family, featuring additional interconnect resources and other user-friendly enhancements.
- XC3000L Family — The XC3000L is identical in architecture and features to the XC3000A family, but operates at a nominal supply voltage of 3.3 V. The XC3000L is the right solution for battery-operated and low-power applications.
- XC3100A Family — The XC3100A is a performance-optimized relative of the XC3000A family. While both families are bit stream and footprint compatible, the XC3100A family extends toggle rates to 370 MHz and in-system performance to over 80 MHz. The XC3100A family also offers one additional array size, the XC3195A.
- XC3100L Family — The XC3100L is identical in architectures and features to the XC3100A family, but operates at a nominal supply voltage of 3.3V.
Fig 5.6 illustrates the relationships between the families. Compared to the original XC3000 family, XC3000A offers additional functionality and increased speed. The XC3000L family offers the same additional functionality, but reduced speed due to its lower supply voltage of 3.3 V. The XC3100A family offers substantially higher speed and higher density with the XC3195A.
Fig 5.6 XC3000 FPGA Families
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Detailed Functional Description
The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Configurable Logic Blocks (CLBs) performs user-specified logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed circuit board traces connecting MSI/SSI packages.
The block logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with metal segments joined by program-controlled pass transistors.
These FPGA functions are established by a configuration program which is loaded into an internal, distributed array of configuration memory cells. The configuration program is loaded into the device at power-up and may be reloaded on command. The FPGA includes logic and control signals to implement automatic or passive configuration. Program data may be either bit serial or byte parallel. The development system generates the configuration program bit stream used to configure the device. The memory loading process is independent of the user logic functions.
Configuration Memory
The static memory cell used for the configuration memory in the Field Programmable Gate Array has been designed specifically for high reliability and noise immunity. Integrity of the device configuration memory based on this design is assured even under adverse conditions. As shown in Figure 5.7 , the basic memory cell consists of two CMOS inverters plus a pass transistor used for writing and reading cell data. The cell is only written during configuration and only read during read back. During normal operation, the cell provides continuous control and the pass transistor is off and does not affect cell stability. This is quite different from the operation of conventional memory devices, in which the cells are frequently read and rewritten.
Fig 5.7 Static Configuration Memory Cell.
It is loaded with one bit of configuration program and controls one program selection in the Field Programmable Gate Array.
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Fig 5.8 Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice of two clocks is available on each die edge. The polarity of each clock line (not each flip- flop or latch) is programmable. A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds.
Summary of I/O Options
- Inputs
- Direct
- Flip-flop/latch
- CMOS/TTL threshold (chip inputs)
- Pull-up resistor/open circuit
- Outputs
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- Direct/registered
- Inverted/not
- 3-state/on/off
- Full speed/slew limited
- 3-state/output enable (inverse)
Configurable Logic Block
The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks arranged in 8 rows and 8 columns. The development system is used to compile the configuration data which is to be loaded into the internal configuration memory to define the operation and interconnection of each block. User definition of CLBs and their interconnecting networks may be done by automatic translation from a schematic-capture logic diagram or optionally by installing library or user macros. Each CLB has a combinatorial logic section, two flip-flops, and an internal control section. In Figure 5.9, There are: five logic inputs (A, B, C, D and E); a common clock input (K); an asynchronous direct RESET input (RD); and an enable clock (EC). All may be driven from the interconnect resources adjacent to the blocks. Each CLB also has two outputs (X and Y) which may drive interconnect networks.
Fig 5.9 Configurable Logic Block
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Altera Complex Programmable Logic devices
Altera has developed three families of chips that fit within the CPLD category: MAX 5000, MAX 7000, and MAX 9000. Here, the discussion will focus on the MAX 7000 series, because it is widely used and offers state-of-the-art logic capacity and speed-performance. MAX 5000 represents an older technology that offers a cost effective solution, and MAX 9000 is similar to MAX 7000, except that MAX 9000 offers higher logic capacity (the industry’s highest for CPLDs).
The general architecture of the Altera MAX 7000 series is depicted in Figure 5.10. It comprises an array of blocks called Logic Array Blocks (LABs), and interconnect wires called a Program mable Interconnect Array (PIA). The PIA is capable of connecting any LAB input or output to any other LAB. Also, the inputs and outputs of the chip connect directly to the PIA and to LABs. A LAB can be thought of as a complex SPLD-like structure, and so the entire chip can be considered to be an array of SPLDs. MAX 7000 devices are available both based in EPROM and EEPROM technology. Until recently, even with EEPROM, MAX 7000 chips could be programmable only “out-of-circuit” in a special-purpose programming unit; however, in 1996 Altera released the 7000S series, which is reprogrammable “in- circuit”.
Fig 5.10 Altera MAX 7000 Series.
The structure of a LAB is shown in Figure 5.11. Each LAB consists of two sets of eight macro cells (shown in Figure 5.12 ), where a macro cell comprises a set of programmable product terms (part of an AND-plane) that feeds an OR-gate and a flip-flop. The flip-flops can be configured as D type, JK, T, SR, or can be transparent. As illustrated in Figure 10, the number of inputs to the OR-gate in a macro cell is variable; the OR-gate can be fed from any or all of the five product terms within the macro cell, and in addition can have up to 15 extra product terms from macro cells in the same LAB. This product term flexibility makes the MAX 7000 series LAB more efficient in terms of chip area because typical logic functions do not need more than five product terms, and the architecture supports wider functions when
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they are needed. It is interesting to note that variable sized OR-gates of this sort are not available in basic SPLDs.
Fig 5.11 Altera MAX 7000 Logic Array Block (LAB).
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Fig 5.13 Altera FLASHlogic CPLD.
In terms of basic structure, FLASH logic is similar to other products already discussed. However, they have one unique feature that stands them apart from all other CPLDs: each PAL-like block, instead of being used for AND-OR logic, can be configured as a block of 10 nsec Static RAM. This concept is illustrated in the lower part of Figure 5.13, which shows one CFB being used as a PAL and another configured as an SRAM. In the SRAM configuration, the PAL block becomes a 128 word by 10 bit read/write memory. Inputs that would normally feed the AND plane in the PAL in this case become address lines, data in, and control signals for the memory. Notice that the flip-flops and tri-state buffers are still available when the PAL block is configured as memory. In the FLASH logic device, the AND- OR logic plane’s configuration bits are SRAM cells that are “shadowed” by EPROM or EEPROM cells. The SRAM cells are loaded with a copy of the non-volatile EPROM or EEPROM memory when power is applied, but it is the SRAM cells that control the configuration of the chip. It is possible to re-configure the chips in-system by downloading new information into the SRAM cells. The SRAM cells’ contents can be written back to the EEPROM, so that non-volatile re-programming (in-circuit) is available.
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Interfacing Memory To a Microprocessor Bus
In order to design the interface, the timing specifications for both the memory and microprocessor must be satisfied. When writing to memory, the setup and hold time specifications for the memory must be satisfied, and when reading from memory, the setup and hold time specifications for the microprocessor bus must be satisfied. If the memory is slow, it may be necessary to insert wait states in the bus cycle. We design the interface between a 486 bus and a small static RAM memory, and then we write code to test the interface timing. We use the static RAM and 486 bus interface models that we have already developed. Figure shows how the bus interface is connected to the static RAM memory.
The memory consists of four static RAM chips, and each RAM chip contains = 32,768 8-bit words. The four chips operate in parallel to give a memory that is 32 bits wide. Data bits 31-24 are connected to the first chip, bits 23-16 to the second chip, etc. The lower 15 bits of the address bus are connected in parallel to all four chips. The system includes a memory controller that generates WE and CS signals for the memory and returns a Rdy signal to the bus interface to indicate completion of a read or write bus cycle. We will assign the address range 0 through 32,767 to the static RAM. In general, a complete 486 system would have a large dynamic RAM memory and I/O interface cards connected to the address and data busses. To allow for expansion to the system, we use an address decoder, so the static RAM is selected only for the specified address range. When an address in the range 0 to 32,767 is detected, the decoder outputs CSI = 1, which activates the memory controller.
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Design of a UART
A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the reception and transmission of information, in a serial and asynchronous way
A UART allows the communication between a computer and several kinds of devices (printer, modem, etc), interconnected via an RS-232 cable
Fig 5.15 Block Diagram
Serial transmission
Data transmission is made by the UART in a serial way, by 11-bit blocks:
- a 0 bit marks the starting point of the block
- eight bits for data
- one parity bit
- a 1 bit marking the end of the block
- The transmission and reception lines should hold a 1 when no data is transmitted
Fig 5.16 Data Transmission in UART
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The first transmitted bit is the LSB (least significant bit) The parity bit is set to 1 or 0, depending on the number of 1's transmitted: if even parity is used, this number should be even; if odd parity is used, this number should be odd. If the chosen parity is not respected in the block, a transmission error should be detected The transmission speed is fixed, measured in bauds
Implementation
A possible entity for the UART is:
Fig 5.17 UART entity
The meaning of signals is:
- parityerr: error during the block reception
- framingerr: format error during the block reception
- overrun: a new data is arrived before reading of the precedent data
- rxrdy: a new data is arrived and it's ready for reading
- txrdy: a new data is ready for sending
- read: reading of the receiver's data is activated
- write: writing of the emitter's data is activated
