ECE 200 Digital Logic Design - Final Exam Review (Qns & Ans) - DU 2025, Exams of Logic

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ECE 200

Digital Logic Design

Final Exam Review

(Questions & Solutions)

Section I – Multiple Choice (8 Questions)

1. In digital logic design, which gate is considered universal because any Boolean function can be implemented using only that gate? A. AND B. OR C. NAND D. XOR ANS: C Rationale: The NAND gate is universal, meaning that any Boolean function can be constructed solely using NAND gates. This makes it a cornerstone in digital circuit synthesis.

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2. Which of the following Boolean algebra laws states that a variable ORed with its complement yields 1? A. Identity Law B. Null Law C. Complementarity Law D. Absorption Law ANS: C Rationale: The Complementarity Law (or Inverse Law) states that for any Boolean variable X, ( X + X' = 1 ). This fundamental relationship is critical in many minimization and simplification procedures.

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3. In a 4-variable Karnaugh map, what is the maximum size of a grouping (or "implicant") that can be formed to simplify a Boolean expression?

C. To select one input from many and forward it to the output D. To perform arithmetic operations ANS: C Rationale: A multiplexer (MUX) is a combinational circuit that selects one of many input signals based on control signals and forwards the selected input to a single output line.

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6. In designing adders for arithmetic operations, which circuit component is used to add two binary digits along with a carry-in? A. Half adder B. Full adder C. Multiplexer D. Encoder ANS: B Rationale: A full adder is designed to add two single binary digits plus an input carry and produce a sum and a carry-out, making it essential in constructing multi-bit arithmetic circuits.

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7. Which error detection method in digital systems works by adding an extra bit so that the total number of 1s is even (or odd)? A. Cyclic Redundancy Check B. Parity Bit Checking C. Hamming Code D. Checksum ANS: B Rationale: Parity bits are appended to data words to ensure that the total number of 1s is even (even parity) or odd (odd parity), making it a simple error detection method.

8. In circuit minimization using the Quine–McCluskey method, what is the primary goal of the algorithm? A. Convert the Boolean expression into a truth table B. Systematically eliminate redundant terms to obtain a minimal sum- of-products form C. Design the physical layout of the logic circuit D. Generate sequential circuit timing diagrams ANS: B Rationale: The Quine–McCluskey method is an algorithmic approach to simplifying Boolean expressions by eliminating redundant terms and identifying prime implicants to achieve a minimal sum-of-products expression.

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Section II – Fill-in-the-Blank (4 Questions)

9. In Boolean algebra, the law that states ( X \cdot 1 = X ) and ( X + 0 = X ) is known as the _______ Law_. ANS: Identity Rationale: The Identity Law establishes that any variable multiplied by 1 or ORed with 0 remains unchanged.

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10. In Karnaugh map simplification, a grouping that covers a minterm that no other grouping covers is known as an _______ prime implicant_. ANS: Essential Rationale: An essential prime implicant covers at least one minterm that is not covered by any other implicant, making it necessary in the minimal expression.

ANS: False Rationale: Although Karnaugh maps become more challenging to use beyond four to six variables, they are still applicable – with careful grouping and sometimes with computer assistance – to functions with more variables.

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15. True or False: Asynchronous sequential circuits rely on global clock signals for state changes. ANS: False Rationale: Asynchronous circuits do not use a global clock; instead, they rely on the immediate propagation of signals and transitions, which distinguishes them from synchronous circuits.

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16. True or False: In digital logic, De Morgan’s laws provide the transformations necessary to convert AND-OR expressions into OR-AND expressions (and vice versa). ANS: True Rationale: De Morgan’s laws state that the complement of a conjunction is the disjunction of the complements, and vice versa, enabling systematic transformations between AND-OR and OR-AND forms.

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Section IV – Multiple Response (4 Questions)

17. Which of the following are considered Boolean algebra laws fundamental to digital logic simplification? (Select all that apply) A. Identity Law B. Complementarity Law C. Distributive Law

D. Absorption Law E. Fourier's Law ANS: A, B, C, D Rationale: The Identity, Complementarity, Distributive, and Absorption Laws are core to Boolean algebra and are used extensively in logic simplification. Fourier’s Law is unrelated to Boolean operations.

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18. When using Karnaugh maps, which of the following features enhance the simplification process? (Select all that apply) A. Adjacency of ones in power-of-two groupings B. Wrapping (toroidal mapping) of the Karnaugh map C. Identification of essential prime implicants D. Using don’t-care conditions to expand groups E. Ignoring the binary representation of variables ANS: A, B, C, D Rationale: Adjacent grouping, map wrapping, essential prime implicant identification, and utilizing don't-care conditions all contribute to effective K-map simplification. Ignoring binary representations would prevent proper grouping.

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19. In the design of sequential circuits, which of the following components are commonly used memory elements? (Select all that apply) A. Latches B. D-type flip-flops C. Registers D. Multiplexers E. Counters

D) External conditions Correct ANS: C) Current input and previous outputs Rationale: Sequential circuits have memory elements that store past states, influencing current outputs. What is the maximum number of states for a 4-bit counter? A) 8 B) 15 C) 16 D) 32 Correct ANS: C) 16 Rationale: A 4-bit counter can represent (2^4 = 16) distinct states. Which logic family is known for its high speed and low power consumption? A) TTL B) CMOS C) ECL D) RTL Correct ANS: B) CMOS Rationale: CMOS technology is widely recognized for its excellent speed-power product. Fill-in-the-Blank Questions A flip-flop is a basic building block of __ circuits. Correct ANS: Sequential Rationale: Flip-flops store binary information, forming the basis of sequential logic circuits. The process of converting a Boolean expression into a logic circuit is called __. Correct ANS: Synthesis Rationale: Synthesis involves creating a circuit that implements the desired Boolean function.

A multiplexer is a device that selects one of many inputs and forwards that input to a single __. Correct ANS: Output Rationale: The function of a multiplexer is to route one input line to an output line based on selection signals. True/False Questions True or False: An XOR gate produces a true output when both inputs are true. Correct ANS: False Rationale: An XOR gate produces a true output only when one input is true and the other is false. True or False: In a combinational circuit, the current output depends solely on the current input values. Correct ANS: True Rationale: Combinational circuits do not have memory; they output based only on current inputs. Multiple Response Questions Which of the following are types of flip-flops? (Select all that apply) A) D Flip-Flop B) JK Flip-Flop C) T Flip-Flop D) Latch Correct ANSs: A) D Flip-Flop, B) JK Flip-Flop, C) T Flip-Flop Rationale: D, JK, and T are distinct flip-flop types, while a latch is a different type of memory element. Which of the following components are necessary for constructing a full adder? (Select all that apply) A) XOR gates

Which configuration of transistors can be used to implement a static RAM cell? A) CMOS B) Bipolar Junction C) Resistor-Transistor Logic D) Diode-Transistor Logic Correct ANS: A) CMOS Rationale: Static RAM cells are typically implemented using CMOS technology for its low power and compact layout. The function of a decoder is to convert binary information from n input lines to a maximum of __ output lines. Correct ANS: (2^n) Rationale: A decoder takes n inputs and decodes them into (2^n) unique outputs. In a synchronous counter, the state changes occur with respect to: A) Input signal B) Clock signal C) Reset signal D) Enable signal Correct ANS: B) Clock signal Rationale: Synchronous counters change states based on clock pulses, ensuring coordinated transitions. What is the primary purpose of a shift register? A) To perform addition B) To store data temporarily C) To shift data serially D) To convert parallel data to serial Correct ANS: C) To shift data serially Rationale: Shift registers are used to shift binary data in and out, facilitating serial communication.

Which of the following can be used to implement a half adder? (Select all that apply) A) NAND gates B) XOR gates C) AND gates D) OR gates Correct ANSs: B) XOR gates, C) AND gates Rationale: A half adder uses an XOR gate for the sum and an AND gate for the carry. The primary advantage of using a programmable logic device (PLD) is: A) Fixed performance B) Customizability for specific applications C) Higher power consumption D) Simplicity of design Correct ANS: B) Customizability for specific applications Rationale: PLDs offer the flexibility to implement various logic functions tailored to specific needs. Multiple Choice Which of the following statements about hazard mitigation in combinational logic circuits is correct? A. Hazards can be entirely eliminated using ideal gates. B. Adding redundant gates can help mitigate static hazards. C. Propagation delay is irrelevant to hazard analysis. D. Dynamic hazards are more easily mitigated than static hazards. ANS: B Rationale: Adding redundant gates (covering all prime implicants) can eliminate static hazards. What is the primary advantage of using a Look-Up Table (LUT) in modern FPGAs? A. Fixed and inflexible logic.

B. Quine-McCluskey Algorithm C. Boolean Algebra Simplification D. Algebraic Manipulation ANS: B Rationale: Quine-McCluskey algorithm is suitable for computer-aided minimization with more than 6 variables. A Mealy machine differs from a Moore machine in that: A. Its output depends only on the current state. B. Its output depends on both current state and current inputs. C. It cannot be implemented using flip-flops. D. It always has fewer states. ANS: B Rationale: Mealy machine outputs depend on current state and inputs. Which property is characteristic of synchronous counters? A. All flip-flops are clocked simultaneously. B. Outputs contain glitches due to propagation delay. C. They are slower than ripple counters. D. They cannot be built using T flip-flops. ANS: A Rationale: In a synchronous counter, all flip-flops receive the clock at the same time. What is the minimal expression of ( F = A'B + AB' + AB )? A. A B. B C. A + B D. A ⊕ B ANS: C Rationale: (A'B + AB' + AB = (A'B + AB') + AB = (A ⊕ B) + AB = A + B).

In a 4-input priority encoder, which output represents ‘invalid input’ when all inputs are zero? A. 11 B. 00 C. 01 D. A ‘valid’ output is used for this condition. ANS: D Rationale: Priority encoders usually have a ‘valid’ output to signify when at least one input is high. Which of the following is a necessary condition for a circuit to be considered as a combinational logic circuit? A. The output only depends on the past and current inputs. B. The output only depends on the present input values. C. The circuit contains memory elements. D. Sequential signal feedback is present. ANS: B Rationale: Combinational circuits must not remember past inputs; outputs depend only on the present inputs. Fill-in-the-Blank A master–slave flip-flop is constructed using two __________ flip-flops and an inverter. ANS: level-triggered Rationale: Master-slave flip-flops use two level-triggered flip-flops cascaded with an inverter. The __________ theorem is used for simplifying Boolean expressions by eliminating redundant terms. ANS: Consensus Rationale: The Consensus theorem helps in removing redundant terms in logic expressions.

Rationale: FPGAs are reprogrammable logic devices with configurable elements. The phenomenon where input changes lead to unwanted output transitions in combinational circuits is called a __________. ANS: hazard Rationale: Hazards refer to unwanted fluctuations due to delays in logic circuits. In a D flip-flop, the output Q always follows the __________ input after the active clock edge. ANS: D Rationale: The Q output of a D flip-flop conforms to the D input after the triggering edge. True/False A Moore machine always requires fewer states than a Mealy machine for any logic function implementation. ANS: False Rationale: Mealy machines often require fewer states, not more. State minimization for sequential circuits is equivalent to finding sets of equivalent states. ANS: True Rationale: State minimization involves merging states with equivalent next-state and output behavior. A synchronous up/down counter can only count up or down at any one time, but not both. ANS: True Rationale: A synchronous up/down counter operates in either up or down mode, depending on the control signal. A multiplexer can be used as a general-purpose logic element capable of implementing any Boolean function.

ANS: True Rationale: A multiplexer can implement any Boolean function by suitable input mapping. Propagation delay in logic gates is a critical factor only in combinational circuits, not in sequential circuits. ANS: False Rationale: Propagation delay affects both combinational and sequential timing, such as setup and hold times. Asynchronous (ripple) carry adders are faster than synchronous (look- ahead) carry adders. ANS: False Rationale: Look-ahead carry adders are faster than ripple carry adders. A Karnaugh map can directly handle incompletely specified functions by assigning don’t-care conditions. ANS: True Rationale: K-maps allow don’t-cares to facilitate minimal sum or product forms. In programmable logic arrays (PLAs), both the AND and OR planes are programmable. ANS: True Rationale: PLAs have programmable AND and OR arrays.