ECE 371 MIDTERM EXAM (A) FALL 2022 NAME____KEY__________________ 1
1. The 8-bit two’s complement Sign and Magnitude representation for the decimal
number –25 is ______________ (show work)
00011001 = 25
11100110
+1
11100111 = -25
2. The diagram below shows a section of a pipelined machine that essentially
functions as a shift register. The registers each have a propagation delay of 5 ns, a
setup time of 2 ns and a hold time of 1 ns. Logic block A has a propagation delay of 2
ns and logic block B has a propagation delay of 3 ns. Calculate the minimum clock
period and the maximum frequency at which this circuit can be clocked with no slack
time. (Think about which stage is the worst case (limiting factor.) (Show all work.)
Tclk-min = TFFpd + TBlock b + Tsu
Tclk-min = 5 ns + 3 ns + 2 ns = 10 ns
FMAX = 1/10 ns = 100 MHz
3. Briefly explain how a Branch Target buffer and two-bit branch prediction reduces
pipeline stalls during execution of a program loop such as the one in Figure 2-9 that
executes many times.
The first time execution reaches the branch at the end of the loop there will be
stalls, because the Branch target address is not known until the EX stage and by
then the processor has fetched two instructions that will be flushed. However, the
Branch target address is put in the Branch Target buffer for future use and the
prediction bits are moved toward taken. The next time execution reaches the
branch instruction there may be stalls, if the prediction bits do not predict taken.
If the prediction bits predict taken, the address in the BTB will be used to fetch
the first instruction of the loop with no stalls. In the last execution of the loop,
the prediction of taken will be wrong, so the instructions fetched from the BTB
access will be cancelled and ths stalls the pipeline while the correct instructions
are fetched (See Text page 78)
