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Module # EELE 414 – Introduction to VLSI Design Page 1
EELE 414 – Introduction to VLSI Design
Module # 2 – MOSFET Operation
- Agenda
- MOSFET Operation
- Device Physics
- MOSFET Structure
- IV Characteristics
- Scaling
- Small Geometry Effects
- Capacitance
- Announcements
- Read Chapter 3
Module # EELE 414 – Introduction to VLSI Design Page 2
MOSFET Operation
- MOSFET
- Metal Oxide Semiconductor Field Effect Transistor
- we need to understand the detailed operation of the MOSFET in order to use it to build larger blocks such as Inverters, NAND gates, adders, etc…
- we will cover the theory of the device physics, energy bands, and circuit operation
- we will do homework to analyze the behavior by hand
- in the real world, we typically use SPICE simulations to quickly analyze the MOSFET behavior
- but we need to understand what SPICE is calculating or:
- we won‟t be able to understand performance problems
- we won‟t be able to troubleshoot (is it the tool, is it the circuit, is it the process?)
Module # EELE 414 – Introduction to VLSI Design Page 3
Semiconductors
- Semiconductors
- a semiconductor is a solid material which acts as an insulator at absolute zero. As the temperature increases, a semiconductor begins to conduct
- a single element can be a semiconductor:
Carbon (C), Silicon (Si)
- a compound material can also form a semiconductors (i.e., two or more materials chemically bonded)
Gallium Arsenide (GaAs), Indium Phosphide (InP)
- an alloy material can also form semiconductors (i.e., a mixture of elements of which one is a metal):
Silicon Germanium (SiGe), Aluminum Gallium Arsenide (AlGaAs)
- Silicon is the most widely used semiconductors for VLSI circuits due to:
- it is the 2nd^ most abundant element (25.7%) of the earth‟s crust (after oxygen)
- it remains a semiconductor at a higher temperature
- it can be oxidized very easily
Module # EELE 414 – Introduction to VLSI Design Page 4
Semiconductors
- Charge Carriers
- since we want to use Si to form electronics, we are interested in its ability to conduct current. A good conductor has a high concentration of charge carriers.
- an electron can be a charge carrier.
- a hole (the absence of an electron) can be a charge carrier.
- “Intrinsic” Silicon means silicon that is pure or it has no impurities. We sometimes called this i-typed Silicon
- Since there are no impurities, the number of charge carriers is determined by the properties of the Silicon itself.
- We can define the Mobile Carrier Concentrations as:
n = the concentration of conducting electrons p = the concentration of conducting holes
- these are defined per unit volume (1/cm^3 )
Module # EELE 414 – Introduction to VLSI Design Page 5
Semiconductors
- Charge Carriers
- Intrinsic Silicon has a carrier concentration of :
ni = 1.45 x 10^10 cm- 3
- notice the units are “carriers per cubic centimeter”
- notice that we give the subscript “i” to indicate “intrinsic”
- this value is dependant on temperature and is defined above at T=300 K (i.e., room temperature)
- there are about 5x10^22 Atoms of Silicon per cubic centimeter in a perfect intrinsic lattice
Module # EELE 414 – Introduction to VLSI Design Page 6
Semiconductors
- Charge Carriers
- The equilibrium of the carriers in a semiconductor always follows the Mass Action Law
- this means there is an equal number of p and n charge carriers in intrinsic Silicon
- Electrons vs. Holes
- electrons have a charge of q =-1.6x10-^19 Coulomb (C)
- holes are the “absence” of electrons in an orbital of an atom. When an electron moves out of an orbital, it leaves a void (or hole). This hole can “accept” another electron
- as electrons move from atom to atom, the holes effectively move in the opposite direction and give the impression of a positive charge moving
2
n p n i
Module # EELE 414 – Introduction to VLSI Design Page 7
Energy Bands
- Energy Bands
- the mobility of a semiconductor increases as its temperature increase.
- Increasing the mobility of a semiconductor eventually turns the material into a conductor.
- this is of interest to electronics because we can control the flow of current
- we can also cause conduction using an applied voltage to provide the energy
- we are interested in how much energy it takes to alter the behavior of the material
- Energy Band Diagrams are a graphical way to describe the energy needed to change the behavior of a material.
Module # EELE 414 – Introduction to VLSI Design Page 8
Energy Bands
- Energy Bands
- Quantum Mechanics created the concept of bands to represent the levels of energy that are present at each “state” of an atom.
- the electrons on an atom occupy these energy states
- For a given number of electrons in an atom, we begin filling in the energy bands from lowest to highest energy until all of the electrons have been used.
- electrons only exist in the bands. By convention, electrons are forbidden from existing in between bands
- there is a finite amount of energy that exists to move an electron from one band to another
- if given enough energy (via heat or E-fields), electrons can receive enough energy to jump to a higher energy band.
Module # EELE 414 – Introduction to VLSI Design Page 9
Energy Bands
Valence Band : the highest range of electron energies where electrons are normally present at absolute zero.
: this is the highest “filled” band
Conduction Band : the range of electron energy sufficient to make the electrons free to accelerate under the influence of an applied electric field (i.e., current).
: this is the lowest “unfilled” band
Module # EELE 414 – Introduction to VLSI Design Page 10
Energy Bands
- Band Gap
- the band gap energy is the energy between the lowest level of the "conduction band" and the top of the "valence band"
- this can be thought of as the amount of energy needed to release an electron for use as current at absolute zero.
Module # EELE 414 – Introduction to VLSI Design Page 11
Energy Bands
- Fermi Level
- the Fermi Level (or energy) represents an energy level that at absolute zero:
- all bands below this level are filled
- all bands above this level are unfilled
- the Fermi Level at room temperatures is the energy at which the probability of a state being occupied has fallen to 0.
- at higher temperatures, in order for an electron to be used as current, it needs to have an energy level close to the Fermi Level
- this can also be thought of as the equilibrium point of the material
Module # EELE 414 – Introduction to VLSI Design Page 12
Energy Bands
- Band Gap Comparisons
- the following shows the relationship of Band Gap energies between insulators, semiconductors, and metals
- notice that the only difference between an insulator and a semiconductor is that the band gap is smaller in a semiconductor.
- notice that there is an overlap between the conduction and valence bands in metals. This means that metals are always capable of conducting current.
Module # EELE 414 – Introduction to VLSI Design Page 19
N-type Doping
- N-type Doping
- this extra electron increases the n-type charge carriers
- we call the additional element that provides the extra electron a Donor
- the concentration of donor charge carriers is now denoted as ND - we call ND the doping concentration of an n-type material
- we can use the Mass Action Law to say:
ntype
i D
D ntype i
p
n
N
N p n
2
2
Module # EELE 414 – Introduction to VLSI Design Page 20
N-type Doping
- N-type Doping
- Doping Silicon can achieve a Donor Carrier Concentration between 10^13 cm-^3 to 10^18 cm-^3
- Doping above 10^18 cm-^3 is considered degenerate (i.e., it starts to reduce the desired effect)
- We give postscripts to denote the levels of doping (normal, light, or heavy)
- Remember that Silicon has a density of ~10^21 atoms per cm
Example:
n- : light doping : ND = 10^13 cm-^3 : 1 in 100,000,000 atoms n : normal doping : ND = 10^15 cm-^3 : 1 in 1,000,000 atoms n+ : heavy doping : ND > 1017 cm-^3 : 1 in 10,000 atoms
Module # EELE 414 – Introduction to VLSI Design Page 21
N-type Doping
- Effect on the Band Structure
- by adding more electron charge carriers to a material, we create new energy states
- by adding more electrons to Silicon, we decrease the energy that it takes for an electron to reach the conduction band
- this moves the Fermi Level (the highest filled energy state at equilibrium) closer to the conduction band
Module # EELE 414 – Introduction to VLSI Design Page 22
N-type Doping
- Effect on the Band Structure
- We can define the Fermi Potential ( F) as the difference between the intrinsic Fermi Level ( Ei ) and the new doped Fermi Level ( EFn )
- note: that Fn has units of volts and is positive since EFn>Ei ,
- note: that Ei and EFn have units of eV, which we convert to volts by dividing by q
- note: we use q=1.6x10-^19 C, which is a positive quantity
- the Boltzmann approximation gives a relationship between the Fermi Level and the charge carrier concentration of a material (a.k.a, the Quasi Fermi Energy).
- This expression relates the change in the Fermi Level (from intrinsic) to the additional charge carriers due to n-type doping.
where, kB = the Boltzmann Constant = 8.62x10-^5 (eV/K) or = 1.38x10-^23 (J/K)
notice that the (EFn - Ei) term in the exponent represents a positive voltage since EFn > Ei
q
E F Ei
F
n n
k T
EE
i
B
Fni
n n e
Module # EELE 414 – Introduction to VLSI Design Page 23
N-type Doping
- Effect on the Band Structure
- if we rearrange terms and substitute n=ND…
- since ND> ni , the natural log is taken on a quantity that is greater than one
- this makes Fn POSITIVE
(^) F i i
D B
B
F i
i
D
kT
EE
i
D
kT
EE
D i
E E
n
N
kT
k T
E E
n
N
e
n
N
N ne
n
n
B
Fni
B
Fni
^
ln
ln
i
B D F
F i F
n
N
q
k T
q
E E
n
n n
ln
Then plug into the Fermi potential
Module # EELE 414 – Introduction to VLSI Design Page 24
P-type Doping
- P-type Doping
- inserting an element into the silicon lattice with a valence of 3 will form 3 covalent bonds but leave one orbital empty
- this is called a hole and since it “attracts an electron”, it can be considered a positive charge with a value of +1.6e-^19 C
Module # EELE 414 – Introduction to VLSI Design Page 25
P-type Doping
- P-type Doping
- this extra electron increases the p-type charge carriers
- we call this type of charge carrier an Acceptor since it provides a location for an electron to go
- the concentration of acceptor charge carriers is now denoted as NA - we call NA the doping concentration of a p-type material
- we can use the Mass Action Law to say:
ptype
i A
ptype A i
n
n
N
n N n
2
2
Module # EELE 414 – Introduction to VLSI Design Page 26
P-type Doping
- Effect on the Band Structure
- by adding more hole charge carriers to a material, we also create new energy states
- holes create new “unfilled” energy states
- this moves the Fermi level down closer to the Valence band
Module # EELE 414 – Introduction to VLSI Design Page 27
P-type Doping
- Effect on the Band Structure
- We again define the Fermi Potential ( F) as the difference between the intrinsic Fermi Level (Ei) and the new doped Fermi Level (EFp)
- we again use the Boltzmann approximation , which gives a relationship between the Fermi Level and the electron concentration of a material.
- notice that the (EFp - Ei) term yields a negative potential since EFp < Ei
- note that for the P-type doping the Fermi level moves down below the original Intrinsic level. This original expression stated the increase in electron energy achieved by the doping.
So we need to swap the p and ni terms to use this equation.
notice that the (Ei - EFp) term in the exponent represents a positive voltage since Ei > EFp
q
E F Ei
F
p p
kT
EE
i
kT
EE
i
B
iFp B
iFp
p ne n p e
Module # EELE 414 – Introduction to VLSI Design Page 28
P-type Doping
- Effect on the Band Structure
- if we rearrange terms and substitute p=NA…
- since NA> ni , the natural log is taken on a quantity that is between 0 and 1
- this makes Fp NEGATIVE
F i A
i B
i Fp A
i B
B
i F
A
i
kT
EE
A
i
kT
EE
i A
E E
N
n
k T
E E
N
n
k T
kT
E E
N
n
e
N
n
n Ne
p
p
B
iFp
B
iFp
^
ln
ln
ln
A
B i F
F i F
N
n
q
kT
q
E E
p
p p
ln
Then plug into the Fermi potential
Module # EELE 414 – Introduction to VLSI Design Page 29
Work Function
- Electron Affinity & Work Function
- another metric of a material is the amount of energy it takes to move an electron into Free Space (E 0 )
Electron Affinity : the amount of energy to move an electron from the conduction band into Free Space.
Work Function : the amount of energy to move an electron from the Fermi Level into Free Space.
q EO EC
q S q EC EF
Module # EELE 414 – Introduction to VLSI Design Page 30
Work Function
- Work Function of Different Materials
- When materials are separate, we can compare their band energies by lining up their Free Space energies
Module # EELE 414 – Introduction to VLSI Design Page 37
MOS Under Bias
- MOS Depletion
- the positive voltage that develops at the Oxide-Semiconductor surface bends the energy bands downward to reflect the decrease in electron energy in this region.
- the thickness of the depletion region is denoted as xd
Module # EELE 414 – Introduction to VLSI Design Page 38
MOS Under Bias
- MOS Depletion
- the depletion depth xd is a function of the surface potential ∅ S
- if we model the holes as a sheet of charge parallel to the oxide surface, then the surface potential (∅ S ) to move the charge sheet a distance xd away can be solved using the Poisson equation.
- the solutions of interest are:
the depth of the depletion region:
the depletion region charge density:
A
Si S F d
qN
x
2
Q q NA xd 2 q NA (^) Si S F
Module # EELE 414 – Introduction to VLSI Design Page 39
MOS Under Bias
- now let's apply a larger positive voltage to the gate
- the positive surface charge in the Oxide is strong enough to pull the minority carrier electrons to the surface.
- this can be seen in the band diagrams by “bending” the mid-gap (or Ei) energy at the surface of the Oxide and semiconductor until it falls below the Fermi Level (EFp)
- the n-type region created near the Oxide-Semiconductor barrier is called the Inversion layer
Module # EELE 414 – Introduction to VLSI Design Page 40
MOS Under Bias
- MOS Inversion
- this region has a higher density of minority carriers than majority carriers during inversion
- by definition, the region is said to be “inverted” when the density of mobile electrons is equal to the density of mobile holes
- this requires that the surface potential has the same magnitude as the bulk Fermi potential,
- as we increase the Gate voltage beyond inversion, more minority carriers (electrons) will be pulled to the surface and increase the carrier concentration
- however, the inversion depth does not increase past its depth at the onset of inversion:
- this means that the maximum depletion depth ( xdm) that can be achieved is given by:
- once an inversion layer is created, the electrons in the layer can be moved using an external E-field
s F
A
Si F dm
qN
x
2 2
F
Module # EELE 414 – Introduction to VLSI Design Page 41
MOSFET Operation
- MOSFET Operation
- we saw last time that if we have a MOS structure, we can use VG to alter the charge concentration at the oxide-semiconductor surface:
Accumulation : VG < 0 : when the majority carriers of the semiconductor are pulled toward the oxide-Si junction
Depletion : VG > 0 (small) when the majority carriers of the Si are pushed away from the oxide-Si junction until there is a region with no mobile charge carriers
Inversion : VG > 0 (large) : when VG is large enough to attract the minority carriers to the oxide-Si junction forming an inversion layer
Module # EELE 414 – Introduction to VLSI Design Page 42
MOSFET Operation
- MOSFET Operation (p-type substrate)
- Inversion is of special interest because we have created a controllable n-type channel that can be used to conduct current.
- these electrons have enough energy that they can be moved by an electric field
- if we applied an E-field at both ends of this channel, the electrons would move
NOTE: In a p-type material, the holes are also charge carriers. But since they exist in all parts of the Si, we can‟t control where the current goes.
We use the minority charge carriers in inversion because we can induce a channel using the MOS structure.
Module # EELE 414 – Introduction to VLSI Design Page 43
MOSFET Operation
- MOSFET Operation (p-type substrate)
- in order to access the channel created by inversion, we add two doped regions at either end of the MOS structure
- these doped regions are of the minority carrier type (i.e., n-type)
- current can flow between these terminals if an inversion is created in the p-type silicon by VG
- since we are controlling the flow of current with a 3rd^ terminal, this becomes a “transistor”
- since we use an E-field to control the flow, this becomes the MOS Field Effect Transistor
Module # EELE 414 – Introduction to VLSI Design Page 44
MOSFET Operation
Gate : The terminal attached to the metal of the MOS structure.
Source : One of the doped regions on either side of the MOS structure. Defined as the terminal at the lower potential (vs. the Drain)
Drain : One of the doped regions on either side of the MOS structure. Defined as the terminal at the higher potential (vs. the Source)
Body : The substrate
NOTE: we often don‟t show the Body connection
Module # EELE 414 – Introduction to VLSI Design Page 45
MOSFET Operation
Length : the length of the channel. This is defined as the distance between the Source and Drain diffusion regions
Width : the width of the channel. Notice that the metal, oxide, source, and drain each run this distance
tox : the thickness of the oxide between the metal and semiconductor
Module # EELE 414 – Introduction to VLSI Design Page 46
MOSFET Operation
Metal : Polysilicon. This is a silicon that has a heavy concentration of charge carriers. This is put on using Chemical Vapor Deposition (CVD). It is naturally conductive so it acts like a metal.
Oxide : Silicon-Oxide (SiO 2 ). This is an oxide that is grown by exposing the Silicon to oxygen and then adding heat. The oxide will grow upwards on the Silicon surface
Semiconductor : Silicon is the most widely used semiconductor.
P-type Silicon : Silicon doped with Boron
N-type Silicon : Silicon doped with either Phosphorus or Arsenic
Module # EELE 414 – Introduction to VLSI Design Page 47
MOSFET Operation
- MOSFET Type
- we can create a MOSFET using either a p-type or n-type substrate. We then can move current between the source and drain using the minority carriers in inversion to form the conduction channel
- we describe the type of MOSFET by describing what material is used to form the channel
N-Channel MOSFET P-Channel MOSFET
- p-type Substrate - n-type Substrate
- n-type Source/Drain - p-type Source/Drain
- current carried in n-type channel - current carried in p-type channel
Module # EELE 414 – Introduction to VLSI Design Page 48
MOSFET Operation
- Enhancement vs. Depletion MOSFETS
Enhancement Type : when a MOSFET has no conduction channel at VG=0v : also called enhancement-mode : we apply a voltage at the gate to turn ON the channel : this is used most frequently and what we will use to learn VLSI
Depletion Type : when a MOSFET does have a conducting channel at VG=0v : also called depletion-mode : we apply a voltage at the gate to turn OFF the channel : we won‟t use this type of transistor for now
Note: We will learn VLSI circuits using enhancement-type, n-channel MOSFETS. All of the principles apply directly to Depletion-type MOSFETs as well as p-channel MOSFETs.
Module # EELE 414 – Introduction to VLSI Design Page 55
Threshold Voltage
- Threshold Voltage
- the threshold voltage depends on the following:
the work function difference between the Gate and the Channel
the gate voltage necessary to change the surface potential
the gate voltage component to offset the depletion region charge
the gate voltage necessary to offset the fixed charges in the Gate-Oxide and Si-Oxide junction
- putting this all together gives us the expression for the threshold voltage at Zero Substrate Voltage
ox
ox
ox
B
T GC F C
Q
C
Q
V (^) 0 2 ^0
GC
2 F
ox
B
C
Q 0
ox
ox
C
Q
Module # EELE 414 – Introduction to VLSI Design Page 56
Threshold Voltage
- Threshold Voltage with Non-Zero Substrate Bias
- sometimes we can't guarantee that the substrate will be zero at all points of the IC:
- when a potential develops in the substrate, it pushes the Source terminal of the MOSFET to a higher potential. We typically describe this as VSB (instead of VBS)
- to predict the effect of a substrate bias voltage (VSB), we must alter the expression for the depletion charge density term:
- this changes the expression for the Threshold Voltage to:
ox
ox ox
B T GC F
C
Q
C
Q
V 2
ox
B ox
B
C
Q
C
Q
Module # EELE 414 – Introduction to VLSI Design Page 57
Threshold Voltage
- Threshold Voltage with Non-Zero Substrate Bias cont…
- VT0 is hard to predict due to uncertainties in the doping concentrations during fabrication. As a result, VT0 is measured instead of calculated.
- this means for a typical transistor, it is a given quantity
- however, the non-zero Substrate Bias is a quantity that still must be considered.
- we want to get an expression for VT that includes VT0 (a given)
- the depletion charge density is a function of the material and the substrate bias:
ox
B B T ox
B B
ox
ox
ox
B T GC F
C
Q Q
V
C
Q Q
C
Q
C
Q
V 2 0 0 0 0
(^) F SB F ox
ASi
ox
B B V
C
qN
C
Q Q
Module # EELE 414 – Introduction to VLSI Design Page 58
Threshold Voltage
- Threshold Voltage with Non-Zero Substrate Bias cont…
- we can separate the material dependant term into its own parameter separate from VSB
where is called the substrate-bias or body-effect coefficient
- this leaves our complete expression for threshold voltage as:
- a few notes on this expression:
- in an n-channel, the following signs apply:
- in a p-channel, the following signs apply
VT VT 0 2 F VSB 2 F
ox
A Si
C
qN
F V SB
Module # EELE 414 – Introduction to VLSI Design Page 59
Threshold Voltage
- Threshold Voltage with Non-Zero Substrate Bias cont…
- the following plot shows an example of threshold dependence on substrate bias for an enhancement-type, n-channel MOSFET
- the threshold voltage increases with Substrate bias. This means as noise gets on the substrate, it takes more energy to create the channel in the MOSFET. This is a BAD thing…
VT VT 0 2 F VSB 2 F
Module # EELE 414 – Introduction to VLSI Design Page 60
MOSFET I-V Characteristics
- MOSFET I-V Characteristics
- we have seen how the Gate-to-Source voltage (VGS) induces a channel between the Source and Drain for current to flow through
- this current is denoted IDS
- remember that this current doesn't flow unless a potential exists between VD and VS
- the voltage that controls the current flow is denoted as VDS
- once again, we start by applying a small voltage and watching how IDS responds
- notice that now we actually have two control variables that effect the current flow, VGS and VDS
- this is typical operating behavior for a 3-terminal device or transistor
- we can use an enhancement n-channel MOSFET to understand the IV characteristics and then directly apply them to p-channel and depletion-type devices
Module # EELE 414 – Introduction to VLSI Design Page 61
MOSFET I-V Characteristics
- MOSFET I-V Characteristics : Cutoff Region
- when VGS < VT, there is no channel formed between the Drain and Source and hence IDS=0 A
- this region is called the Cutoff Region
- this region of operation is when the Transistor is OFF
Module # EELE 414 – Introduction to VLSI Design Page 62
MOSFET I-V Characteristics
- MOSFET I-V Characteristics : Linear Region
- When VGS > VT, a channel is formed. IDS is dependant on the VDS voltage
- When VDS = 0v, no current flows
Module # EELE 414 – Introduction to VLSI Design Page 63
MOSFET I-V Characteristics
- MOSFET I-V Characteristics : Linear Region
- If VGS > VT and VDS > 0, then a current will flow from the Drain to Source (IDS)
- the MOSFET operates like a voltage controlled resistor which yields a linear relationship between the applied voltage (VDS) and the resulting current (IDS)
- for this reason, this mode of operation is called the Linear Region
- this region is also sometimes called the triode region (we'll use the term "linear")
- VDS can increase up to a point where the current ceases to increase linearly (saturation)
- we denote the highest voltage that VDS can reach and still yield a linear increase in current as the saturation voltage or VDSAT
Module # EELE 414 – Introduction to VLSI Design Page 64
MOSFET I-V Characteristics
- MOSFET I-V Characteristics : Linear Region
- when a voltage is applied at VD, its positive charge pushes the majority charge carriers (holes) that exist at the edge of the depletion region further from the Drain.
- as the depletion region increases, it becomes more difficult for the Gate voltage to induce an inversion layer. This results in the inversion layer depth decreasing near the drain.
- as VD increases further, it eventually causes the inversion layer to be pinched-off and prevents the current flow to increase any further.
- this point is defined as the saturation voltage (VDSAT)
- from this, we can define the linear region as:
VGS>VT
0 < VDS < VDSAT
Module # EELE 414 – Introduction to VLSI Design Page 65
MOSFET I-V Characteristics
- MOSFET I-V Characteristics : Linear Region
- the Drain to Source current (IDS) is given by the expression:
- where:
un = electron surface mobility (units in cm^2 /V·s) Cox = Unit Oxide Capacitance (units in F/cm^2 ) W = width of the gate L = length of the gate
- remember this expression is only valid when :
VGS>VT
0 < VDS < VDSAT
2 0 ^2
GS T DS DS
n ox
DS V V V V
L
uC W
I linear
A note on electron mobility ( un ):
un relates the drift velocity to the applied E-field
Drift velocity is the average velocity that an electron can attain due to an E-field.
We are interested in Drift Velocity because it tells us how fast the electron can get from the Source to the Drain.
Since current is defined as I=∆Q/ ∆t, un relates how much charge can move in a given area per-time and per E-field
Module # EELE 414 – Introduction to VLSI Design Page 66
MOSFET I-V Characteristics
- MOSFET I-V Characteristics : Linear Region
- what is linear about this equation?
- most of the parameters are constants during evaluation. They are sometimes lumped into single parameters
or
- Notice that W and L are parameters that the designers have control over. Most of the other parameters are defined by the fabrication process and are out of the control of the IC designer.
2 0 ^2
GS T DS DS
n ox
DS V V V V
L
uC W
I linear
k ' un Cox
2
DS VGSVT VDSVDS
L
kW
I linear
L
W
k un Cox ^2
DS 2 2 VGSVT 0 VDSVDS
k
I linear
Module # EELE 414 – Introduction to VLSI Design Page 73
MOSFET I-V 2nd Order Effects
- Substrate Bias Effect
- another effect that the 1st order IV equations don't model is substrate bias
- we have assumed that the Silicon substrate is at the same potential as the Source of the MOSFET
- if this is not the case, then the Threshold Voltage may increase and take more energy to induce a channel
- we've already seen how we can model the change in threshold voltage due to substrate bias:
- for the IV equations to accurately model the substrate bias effect, we must use VT instead of VT
VT VT 0 2 F VSB 2 F
2
DS VGSVTVDSVDS
k
I linear
DS ^ VGSVT ^ ^ VDS
k
I
sat
1
2
Module # EELE 414 – Introduction to VLSI Design Page 74
Scaling Theory
- What is Scaling?
- Moving VLSI designs to new fabrication processes
- Shrinking the size of the circuitry
First Planar Integrated Circuit Two Transistors
Pentium 4 Processor 42 Million Transistors
Itanium 2 Dual Processor 1.7 Billion Transistors
Module # EELE 414 – Introduction to VLSI Design Page 75
Scaling Theory
- Improve Performance
- Increase Transistor Density
- Reduce cost per transistor & size of system
- Reduce Power
- Smaller transistors require less supply voltage
300mm wafer
Module # EELE 414 – Introduction to VLSI Design Page 76
Scaling Theory
- Scaling Predictions
- In 1965, Gordon Moore of Intel predicted the exponential growth of the number of transistors on an IC.
- Transistor count will doubled every 2-3 years
- Predicting >65,000 transistors in 1975
Moore’s Prediction (1965)
Module # EELE 414 – Introduction to VLSI Design Page 77
Scaling Theory
- More than just a prediction
- Transistor count has doubled every 26 months for the past 30 years
- Today this trend is used to target future process performance and prepare necessary infrastructure (Design Tools, Test, Manufacturing, Engineering Skills, etc…)
Module # EELE 414 – Introduction to VLSI Design Page 78
Scaling Theory
- Timeline of Major Events
First Integrated Circuit (Noyce/Fairchild & Kilby/Texas Instruments)
First Transistor (Bell Labs)
Noyce and Moore Form Intel
Intel Introduces the 4004, 1st single chip u P (2300 transistors)
Intel Ships 1st^ Billion Transistor u P
Module # EELE 414 – Introduction to VLSI Design Page 79
Scaling Theory
X Y
Chip Area for a Circuit (A) scales following : 1 S^2
Note: In addition, the die sizes have increased steadily, allowing
more transistors per die
A
1 1 S S
S
S
A
Module # EELE 414 – Introduction to VLSI Design Page 80
Full Scaling
- Full Scaling (Constant-Field)
- Reduce physical size of structures by 30% in the subsequent process
W = Width of Gate L = Length of Gate tox = thickness of Oxide xj = depth of doping
- Reduce power supplies and thresholds by 30%
- we define: S ≡ Scaling Factor > 1
- Historically, S has come in between 1.2 and 1. for the past 30 years
- sometimes we use √2 = 1.4 for easy math
Module # EELE 414 – Introduction to VLSI Design Page 81
Full Scaling
- Full Scaling (Constant Field)
- The following quantities are altered during fabrication
- we use a prime („) to denote the new scaled quantity
- Note that the doping concentration has to be increased to keep achieve the desired Fermi level movement due to doping since the overall size of the junction is reduced
Before After Quantity Scaling Scaling
Channel Length L L’ = L/S Channel Width W W’ = W/S
Gate Oxide Thickness tox tox’ = tox/S
Junction depth xj xj’ = xj/S
Power Supply Voltage VDD VDD’ = VDD/S Threshold Voltage VT0 VT0’ = VT0/S
Doping Densities NA NA’ = NA•S
Module # EELE 414 – Introduction to VLSI Design Page 82
Full Scaling
- Scaling Effect on Device Characteristics : Linear Region
- by scaling tox , we effect Cox :
- since then
- The voltages VGS, VTO, and VDS also scale down by S, which creates a1/S^2 in this expression:
- which results in:
IDSlin scales down by S, this is what we wanted!!!
ID
+
VDS
-
ox ox
ox ox
ox ox
ox
ox SC
t
S
S
t t
C
'
'
L
W
k un Cox
0 ^2 ' 2 2 0 ^2
DS GS T DS DS DS VGSVT VDSVDS
S
Sk
V V V V I
k
I
linear linear
Sk
L
W
k un Cox
'
S
I
I linear linear
DS
DS
'
Module # EELE 414 – Introduction to VLSI Design Page 83
Full Scaling
- Scaling Effect on Device Characteristics : Saturation Region
- again, k effects IDS
- which gives
IDSsat scales down by S, this is what we wanted!!!
ID
+
VDS
-
2 2 0
(^2) ' 0
DS 2 GS T DS 2 GS T
V V
S
Sk
V V I
k
I SAT SAT
S
I
I SAT SAT
DS
DS
'
Module # EELE 414 – Introduction to VLSI Design Page 84
Full Scaling
- Scaling Effect on Device Characteristics : Power
- Static Power in the MOSFET can be described as:
- both quantities scale by 1/S
Power scales down by S^2 , this is great!!!
ID
+
VDS
-
P IDS VDS
S
P
S
V
S
I
P DS^ DS
Module # EELE 414 – Introduction to VLSI Design Page 91
Scaling Choices
- So Which One Do We Choose?
- Full Scaling is great, but sometimes impractical.
- Constant Voltage can actually be worse from a performance standpoint
- We actually see a hybrid approach. Dimensions tend to shrink each new generation. Then the voltages steadily creep in subsequent designs until they are in balance. Then the dimensions will shrink again.
- Why scale if it is such a pain?
- the increase in complexity per area is too irresistible.
- it also creates a lot of fun and high paying jobs.
Full Constant-V Quantity Scaling Scaling Cox'^ S S
IDS'^ 1/S S
Power' 1/S^2 S
Power Density' 1 S^3
Module # EELE 414 – Introduction to VLSI Design Page 92
Scaling Trends
DD ds
V
I
- How Does Scaling Effect AC Performance?
- Assume Full Scaling
- Resistance (R)
Device Resistance ( R ) remains constant : 1
R
Ids
+
VDD
-
S
S
R
OK
Module # EELE 414 – Introduction to VLSI Design Page 93
Scaling Trends
ox
W L
t
- How Does Scaling Effect AC Performance?
- Total Gate Capacitance (C)
Gate Capacitance ( C ) scales following : 1 S
Length C
Width
tox
S S
S
C
Good!
Module # EELE 414 – Introduction to VLSI Design Page 94
Scaling Trends
R C
- How Does Scaling Effect AC Performance?
Gate Delay ( ) scales following : 1 S
1 (^1) S
Source
Gate Drain
Vo
R
C
Vi
Good!
Module # EELE 414 – Introduction to VLSI Design Page 95
Scaling Trends
- How Does Scaling Effect AC Performance?
Clock Frequency (f) scales following : S
f
1
1 S
f
Source
Gate Drain
Good!
Module # EELE 414 – Introduction to VLSI Design Page 96
Scaling Trends
C V ^2 f
- How Does Scaling Effect AC Performance?
- Dynamic Power Consumption (P)
Dynamic Power (P) scales following : 1 S^2
P
2 (^1 1) S S S
P
VDD
Ip
In
Great!!!
Module # EELE 414 – Introduction to VLSI Design Page 97
Does Scaling Work?
- How accurate are the predictions?
- For three decades, the scaling predictions have tracked well
Year
1
10
1965 1970 1975 1980 1985 1990 1995 2000 2005
Feature Size (
m)
10 6 3 1.5 (^1) 0.8 (^) 0.
0.250.
Feature Sizes have been reduced by >30%
Module # EELE 414 – Introduction to VLSI Design Page 98
Does Scaling Work?
- How accurate are the predictions?
Year
Transistors
4004
80088080
8086
80286 Intel
Intel486 Pentium
Pentium ProPentium II
Pentium IIIPentium 4
1,
10,
100,
1,000,
10,000,
100,000,
1,000,000,
1970 1975 1980 1985 1990 1995 2000
Year
1
10
100
1,
10,
1970 1975 1980 1985 1990 1995 2000 2005
4004 8008 8080 8086 80286 Intel Intel Pentium Pentium Pro/II/III Pentium 4
Clock Speed (MHz)
Transistor Count has increased exponentially
Clock Rates have improved >43%
Module # EELE 414 – Introduction to VLSI Design Page 99
Can We Keep Scaling?
- Why not just keep scaling?
- If it was easy, we wouldn‟t have jobs!
- each time we get smaller, a couple new major problems arise.
- Over the years, we have a list of issues that we call “Small Geometry Effects” that have posed a barrier to future scaling.
- But until now, all of the problems have been solved with creative engineering and we continue on to the next process.
- You will need to solve the problems in the next generation of process sizes. Good luck!
Module # EELE 414 – Introduction to VLSI Design Page 100
Small Geometry Challenges
Short Channel Effects
- a MOSFET is called a short channel device when the channel length is close to the same size as the depletion region thickness (L≈ xdm). It can also be defined as when the effective channel length Leff is close to the same as the diffusion depth (Leff≈ xj)
Velocity Saturation
- as the device gets smaller, the relative E-field energy tends to increase and the carriers in the channel can reach higher and higher speeds.
- the long channel equations (i.e., the 1st^ order IV expressions) shows a linear relationship between the E-field and the velocity of the carrier.
- however, at a point, the carriers will reach a maximum speed due to collisions with other electrons and other particles in the Silicon
- At this point, there is no longer a linear relationship between the applied E-field (VDS) and the carrier velocity, which ultimately limits the increase in IDS
- we can model this effect by altering the electron mobility term, un
where is an empirical coefficient
( )^0
GS T
n n
V V
u
u eff
Module # EELE 414 – Introduction to VLSI Design Page 101
Small Geometry Challenges
Subthreshold Leakage
- we‟ve stated that when VGS<VT, there is no inversion in the channel and hence, no charge carriers to carry current from the Drain to Source
- this transition from no-inversion to inversion doesn‟t happen instantaneously
- there is a small amount of current that does flow when VGS<VT.
- we call this current Subthreshold leakage current.
- as devices get smaller, this current has become a non-negligible quantity.
- current in this region follows the relationship:
- lowering the VT0 makes this problem worse
0 e^1 e
gs t ds T T
V V V nv v I (^) ds Ids
Vt
Sub- threshold Slope
Sub- threshold Region
Saturation Region Vds^ = 1.
Ids
Vgs
0 0.3 0.6 0.9 1.2 1.5 1.
10 pA
100 pA
1 nA
10 nA
100 nA
1 A
10 A
100 A
1 mA
Module # EELE 414 – Introduction to VLSI Design Page 102
Small Geometry Challenges
Oxide Breakdown
- the Oxide in a MOSFET serves as an insulator between the Gate electrode and the induced channel in the semiconductor
- as tox gets thinner and thinner, it becomes difficult to grow a planar surface. The thin parts of the non-planar oxide can be so thin that they will short out to the semiconductor
- another problem is that electrons can be excited enough in the Gate to have the energy to jump through the oxide.
- this effectively shorts the Gate to the Source/Drain
e
Module # EELE 414 – Introduction to VLSI Design Page 109
Small Geometry : Interconnect
- Interconnect Delay
- Device delay scales following 1/S
- Interconnect delay scales following S^2
Interconnect Delay Dominates below 0.25um
Module # EELE 414 – Introduction to VLSI Design Page 110
Small Geometry : Interconnect
w t
- Interconnect Delay
- DSM Interconnect doesn‟t full scale due to resistance:
- Interconnect structures are becoming “tall”
- Moving up the Z-axis decreases density
R
Module # EELE 414 – Introduction to VLSI Design Page 111
Small Geometry : Interconnect
- Interconnect Delay
- Repeaters are used to make the “delay vs. length” linear
- Repeaters take power
- Repeaters require diffusion layer access
Module # EELE 414 – Introduction to VLSI Design Page 112
Small Geometry : Interconnect
- On-Chip vs. Off-Chip Performance Mismatch
- On-Chip and Off-Chip Features are not scaling at the same rate
On-Chip
- f > 4GHz
- signal count scales exponentially
- Cheap
Off-Chip
- f < 2GHz
- signal count scales linearly (if that!)
- Expensive
Module # EELE 414 – Introduction to VLSI Design Page 113
Small Geometry : Interconnect
- On-Chip vs. Off-Chip Performance Mismatch
- Getting data off-chip is the system bottleneck
Module # EELE 414 – Introduction to VLSI Design Page 114
Small Geometry : Power
- Power Consumption
- Dynamic Power scales at 1/S^2 under “Full Scaling” but…
- Full Scaling is impractical so we don‟t get full 1/S^2 scaling
- Die sizes are increasing ~25% per generation
2000 Prediction (^) Actual
Module # EELE 414 – Introduction to VLSI Design Page 115
Small Geometry : Power
- Power Consumption
- Lowering VT0 and VDD reduces dynamic power but…
- Leakage current increases exponentially
Approaching 50% in DSM
Module # EELE 414 – Introduction to VLSI Design Page 116
Small Geometry : Power
- Power Consumption
- We‟re now breaking the 100W mark @ 40W/cm^2
- Distribution and Cooling become very difficult (if not impractical)
Module # EELE 414 – Introduction to VLSI Design Page 117
MOSFET Capacitance
- MOSFET Capacitance
- We have looked at device physics of the MOS structure
- We have also looked at the DC I-V characteristics of the MOS Transistors
- We have not looked at AC performance
- Capacitance is the dominating imaginary component on-chip (i.e., we don't really have inductance)
- the Capacitances of a MOSFET are considered parasitic
- "parasitic" means unwanted or unintentional. They are unavoidable and a result of fabricating the devices using physical materials.
- we can use the capacitances of the MOSFET to estimate factors such as rise time, delay, fan-out, and propagation delay
Module # EELE 414 – Introduction to VLSI Design Page 118
MOSFET Capacitance
- MOSFET Capacitance
- Capacitance = Charge / Volt = (C/V)
- as we've seen, the charge in a semiconductor is a complex, 3-dimensional, distribution due to the materials, doping, and applied E-field
- we develop simple approximations for the MOSFET capacitances for use in hand calculations
- we define each of the following lumped capacitance for an AC model of the transistors
- each capacitance will have multiple contributions and different values depending on the state of the transistor (i.e., cutoff, linear, saturation)
Module # EELE 414 – Introduction to VLSI Design Page 119
MOSFET Capacitance
- MOSFET Dimensions
- We need to define the geometric parameters present in the MOSFET structure
Mask Length
- we draw a gate length during fabrication
- we call this the Drawn Length , LM
- in reality, the diffusion regions extend slightly under the gate by a distance, LD
- this is called overlap
- the actual gate length (L) is given by:
L LM 2 LD
Module # EELE 414 – Introduction to VLSI Design Page 120
MOSFET Capacitance
W = Channel Width tox = Oxide thickness xj = diffusion region depth Y = diffusion region length
- Channel-Stop Implants
- in order to prevent the n+ diffusion regions from adjacent MOSFETS from influencing each other, we use "channel-stop implants"
- this is a heavily doped region of opposite typed material (i.e., p+ for an n-type)
- these electrically isolate each transistor from each other
