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XOR and XNOR Gates: VHDL Approach for Logic Design, Summaries of Logic

Franklin County Career and Technology CenterLogic

The characteristics of XOR and XNOR gates, their symbols, Boolean equations, and truth tables. It also demonstrates how to use these gates in combinational logic design using the VHDL approach. instructions on how to set up a project in Xilinx Vivado and implement XOR and XNOR gates. It includes exercises to fill in truth tables for all the gates by observing the inputs/outputs on the programmed board.

What you will learn

  • How are XOR and XNOR gates used in combinational logic design?
  • What are some common applications of XOR and XNOR gates?
  • What is the difference between XOR and XNOR gates?
  • What are the characteristics of XOR and XNOR gates?
  • How to implement XOR and XNOR gates using VHDL in Xilinx Vivado?

Typology: Summaries

2021/2022

Uploaded on 09/12/2022

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EXPERIMENT 4
XOR and XNOR Gates with
Applications
OBJECTIVES:
Examining the characteristics of XOR and XNOR gates.
Demonstrate applications of XOR and XNOR gates
Learn to use the VHDL approach to combinational logic design.
MATERIALS:
Xilinx Vivado software, student or professional edition V2018.2 or higher.
IBM or compatible computer with Pentium III or higher, 128 M-byte RAM or more, and 8
G-byte Or larger hard drive.
BASYS 3 Board.
DISCUSSION:
So far we have studied five basic types of gates: AND, OR, NAND, NOR and NOT. In some applications,
it is convenient to use two other types of gates: XOR and XNOR. The XOR and XNOR gates have their
own symbols and unique characteristics. Common applications for XOR and XNOR gates are:
comparators, switchable inverter/buffers, parity generator/checkers and adder/subtractor. They can
also be used to simplify Boolean equations.
We will first discuss the properties of XOR and XNOR having two inputs.
Gate Characteristics:
1. The XOR Gate
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Download XOR and XNOR Gates: VHDL Approach for Logic Design and more Summaries Logic in PDF only on Docsity!

EXPERIMENT 4

XOR and XNOR Gates with

Applications

OBJECTIVES:

 Examining the characteristics of XOR and XNOR gates.  Demonstrate applications of XOR and XNOR gates  Learn to use the VHDL approach to combinational logic design.

MATERIALS:

 Xilinx Vivado software, student or professional edition V2018.2 or higher.  IBM or compatible computer with Pentium III or higher, 128 M-byte RAM or more, and 8 G-byte Or larger hard drive.  BASYS 3 Board.

DISCUSSION:

So far we have studied five basic types of gates: AND, OR, NAND, NOR and NOT. In some applications, it is convenient to use two other types of gates: XOR and XNOR. The XOR and XNOR gates have their own symbols and unique characteristics. Common applications for XOR and XNOR gates are: comparators, switchable inverter/buffers, parity generator/checkers and adder/subtractor. They can also be used to simplify Boolean equations.

We will first discuss the properties of XOR and XNOR having two inputs.

Gate Characteristics:

1. The XOR Gate

Symbol Boolean Equation Truth Table

For a 2-input XOR gate, the output is High when the inputs are unequal.

The output is Low when the inputs are equal. The Boolean equation for

a 2-input XOR gate can be abbreviated as:

However, the function definition remains the same.

  1. Open Xilinix Vivado.
  2. In the Xilinx-Project Navigator window, Quick start, New Project.
  3. Name the project.
  4. Choose “RTL Project” and check the “Do not specify sources at this time” as we will configure all the settings manually through the navigator from inside the project.
  1. Select New Source… and the New window appears. In the New window, choose Schematic, type your file name (such as source_1 ) in the File Name editor box, click on OK, and then click on the Next button.

Then Choose Finish.

  1. The Define Module Window that will appear, we will choose the input and output labels for the gates under investigation in this experiment.
  2. In the “source_1.vhd” created file, type the gates equivalent VHDL code for the XOR and XNOR gates between the “begin” and “end Behavioral” as follows and then save the file.
  1. The implementation errors window will appear if any or the successfully completed window. From this window select “Generate Bitstream” and then OK. This will make the software generate “.bin” file to be used in programing the hardware BAYAS 3.
  2. The next window will appear in which choose “Open Hardware Manger”, connect the Hardware Kit to the USB port and then press OK.
  1. A green tab will appear in the top of the Vivado window, from which choose “open target” to program the hardware.
  2. From the window appears, select the “.bin” file from the Project you

create by browsing for the generated “.bit file” under the “.runs” folder and program

the board then press OK.

  1. Fill in the following truth tables for all the gates by observing the inputs/outputs on the programmed board.

A. XOR Gate

Truth Table (1)

A B C X

0^1

Symbol

Boolean Equation

Section 2 XOR gates used in a comparator:

  1. Repeat section 1 from step 1 to 6.
  2. The Define Module Window that will appear, we will choose the input and output labels for the gates under investigation in this experiment.
  3. In the “source_1.vhd” created file, type the gates equivalent VHDL code for the XOR and XNOR gates between the “begin” and “end Behavioral” as follows and then save the file.
  1. Next, we need to add To add a constraint file with the”.xdc” extension, as following: Go to “Flow Navigator” and from “Project Manager” select “Add Sources” then “Add or create constraints”. Next, choose “Create File” and enter the file name “lab_2” then “OK” followed by “Finish”.
  1. The next window will appear in which choose “Open Hardware Manger”, connect the Hardware Kit to the USB port and then press OK.
  2. A green tab will appear in the top of the Vivado window, from which choose “open target” to program the hardware.

10. From the window appears, select the “.bin” file from the Project you create

by browsing for the generated “.bit file” under the “.runs” folder and program the board

then press OK.

  1. Fill in the following truth tables for all the gates by observing the inputs/outputs on the programmed board.
  1. The Define Module Window that will appear, we will choose the input and output labels for the gates under investigation in this experiment.
  2. In the “source_1.vhd” created file, type the gates equivalent VHDL code for the gates between the “begin” and “end Behavioral” as follows and then save the file.
  1. Next, we need to add To add a constraint file with the”.xdc” extension, as following: Go to “Flow Navigator” and from “Project Manager” select “Add Sources” then “Add or create constraints”. Next, choose “Create File” and enter the file name “lab_2” then “OK” followed by “Finish”.
  2. Repeat section 1 from step 10 to 15.
  3. Fill in the following truth tables for all the gates by observing the inputs/outputs on the programmed board.