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Material Type: Exam; Professor: Gaede; Class: VLSI HARDWARE DESC LANG/MODL/S; Subject: Computer Engineering; University: University of Alabama - Huntsville; Term: Spring 2003;
Typology: Exams
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Electrical and Computer Engineering
Electrical and Computer Engineering
VHDL Problem Statement
Electrical and Computer Engineering
VHDL
use ieee.std_logic_unsigned.all; entity UPCOUNT is port ( CLOCK, RESETN, E : in std_logic; Q : out std_logic_vector (3 downto 0)); end UPCOUNT; architecture BEHAVIOR of UPCOUNT is signal COUNT : std_logic_vector (3 downto 0); begin process (CLOCK, RESETN) begin if RESETN = 0 then COUNT <= 0000 ; elsif (CLOCK event and CLOCK = 1 ) then if E = 1 then COUNT <= COUNT + 1; else COUNT <= COUNT; end if; end process; Q <= COUNT; end BEHAVIOR;
Electrical and Computer Engineering
VHDL Problem Solution
use ieee.std_logic_unsigned.all;
entity UPCOUNT is generic (N : integer); port ( CLOCK, RESETN, E : in std_logic; LD : in std_logic; LD_INPUT : in std_logic_vector(N_1 downto 0); Q : out std_logic_vector (N-1 downto 0)); end UPCOUNT;
Electrical and Computer Engineering
Synthesis Style Model
entity WIDGET is Port (A, B : in SIGNED (0 to 2); CLK, RESET : in std_logic; Z : out SIGNED(0 to 2)); end WIDGET; architecture EXAMPLE of WIDGET is begin process (CLK, RESET) begin if (RESET = 1 then) Z <= 0 ;โ elsif (CLK = 1 ) then Z <= A nor B; end if; end process; end EXAMPLE;
Electrical and Computer Engineering
More Synthesis Style
Qu es t io n:
What ki nd of hardw are elem ent wi ll be inf erred by a sy nt hes is t ool fr om th e f oll owin g mo del?
An s w er:
Sy nopsy s : A la t c h, s i nc e E VE NT is n t pre s ent.
Leonard o: A fl ip -f lo p, s in c e EV ENT is i mp l ie d.
Electrical and Computer Engineering
Second Synthesis Style Model
entity WIDGET is Port (A, B : in SIGNED (0 to 2); CLK : in std_logic; Z : out SIGNED(0 to 2)); end WIDGET; architecture EXAMPLE of WIDGET is begin process (CLK) begin if (CLK = โ1') then Z <= A nor B; end if; end process; end EXAMPLE;
Electrical and Computer Engineering
Scheduling Example
entity SCHED2 is port (A, B, C, D, E, F: in INTEGER; CLK : in BIT; W, X, Y: out INTEGER); end SCHED2; architecture HIGH_LEVEL of SCHED2 is signal Z: INTEGER; begin X <= (A โ B) * C * D; Y <= (A * B) + (E + F)/D; W <= (C + F) * B end HIGH_LEVEL;
Electrical and Computer Engineering
ALAP Scheduling Example Answer
Step Ready List Scheduled Items
n {3, 7, 9} 3, 7
n-1 {9, 1, 2, 4,
6, 8} 9, 1
n-2 {2, 4, 6, 8} 2, 4
n-3 {6, 8} 6, 8
n-4 {5} 5
So, n = 5.
--
A B
/
+
E F
+
*** +**
A B C D
X Y
D C F
B
W
1
2
3
4
5
6
7
8
9
S
S
S
S
S
Electrical and Computer Engineering
Left Edge Algorithm
A B C D E F G H I J K L S1 X X X S2 X X X X X S3 X X X X X S4 X X X X X S5 X X X X X
D C G E J B H F A I L K S1 X X X S2 X X X X X S3 X X X X X S4 X X X X X S5 X X X X X
R1 R2 R3 R4 R S1 D C G - - S2 B C G E J S3 B H G F J S4 B I L F A S5 K I L F A
Electrical and Computer Engineering
VHDL Modeling
Sample input/output sequences are given below.
Electrical and Computer Engineering
VHDL Modeling Answer
Electrical and Computer Engineering
VHDL Modeling Answer (Continued)
when S6 => if (I = '0') then STATE <= S1; else STATE <= S2; end if; when S7 => if (I = '0') then STATE <= S1; else STATE <= S2; end if; end case; end if; end process NEXT_STATE;
Electrical and Computer Engineering
VHDL Modeling Answer (Continued)
OUTPUT: process (STATE) begin case STATE is when S7 => O <= '1'; when others => O <= '0'; end case; end process OUTPUT; end FSM_RTL;
Electrical and Computer Engineering
Implementation Medium Choice
