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Fundamental Of Digital logic with verilog design
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2.1. The proof is as follows:
(x + y) · (x + z) = xx + xz + xy + yz = x + xz + xy + yz = x(1 + z + y) + yz = x · 1 + yz = x + yz
2.2. The proof is as follows:
(x + y) · (x + y) = xx + xy + xy + yy = x + xy + xy + 0 = x(1 + y + y) = x · 1 = x
2.3. Proof using Venn diagrams:
x y
z
x y
z
x y
z
x x + y
x + y ⋅ z ( x + y ) ( x + z )
y ⋅ z x + z
x y
z
x y
z
x y
z
2.4. Proof of 15a using Venn diagrams:
x y
x y
x ⋅ y
y
x ⋅ y
x ⋅ y
x y
x y
x y
x
A similar proof is constructed for 15b.
2.5. Proof using Venn diagrams:
x 1 + x 2
x 1 x 2
x 3
x 1 x 2
x 3
x 1 + x 2 + x 3
x 1 x 2
x 3
( x 1 + x 2 + x 3 ) ⋅( x 1 + x 2 + x 3 )
x 1 x 2
x 1 + x 2 + x 3
x 3
2.8. Timing diagram of the waveforms that can be observed on all wires of the circuit:
x 2
x 1 x 3
A
B
C
D
f
x 2
x 1
x 3
f
A
B
C
D
2.9. Starting with the canonical sum-of-products for f get
f = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 = x 1 (x 2 x 3 + x 2 x 3 + x 2 x 3 + x 2 x 3 ) + x 2 (x 1 x 3 + x 1 x 3 + x 1 x 3 + x 1 x 3 ) +x 3 (x 1 x 2 + x 1 x 2 + x 1 x 2 + x 1 x 2 ) = x 1 (x 2 (x 3 + x 3 ) + x 2 (x 3 + x 3 )) + x 2 (x 1 (x 3 + x 3 ) + x 1 (x 3 + x 3 )) +x 3 (x 1 (x 2 + x 2 ) + x 1 (x 2 + x 2 )) = x 1 (x 2 · 1 + x 2 · 1) + x 2 (x 1 · 1 + x 1 · 1) + x 3 (x 1 · 1 + x 1 · 1) = x 1 (x 2 + x 2 ) + x 2 (x 1 + x 1 ) + x 3 (x 1 + x 1 ) = x 1 · 1 + x 2 · 1 + x 3 · 1 = x 1 + x 2 + x 3
2.10. Starting with the canonical product-of-sums for f can derive:
f = (x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 ) · (x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 ) = ((x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 ))((x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )) · ((x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 ))((x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )) = (x 1 + x 2 + x 3 x 3 )(x 1 + x 2 + x 3 x 3 ) · (x 1 + x 2 + x 3 x 3 )(x 1 + x 2 x 2 + x 3 ) = (x 1 + x 2 )(x 1 + x 2 )(x 1 + x 2 )(x 1 + x 3 )
= (x 1 + x 2 x 2 )(x 1 + x 2 x 3 ) = x 1 (x 1 + x 2 x 3 ) = x 1 x 1 + x 1 x 2 x 3 = x 1 x 2 x 3
2.11. Derivation of the minimum sum-of-products expression:
f = x 1 x 3 + x 1 x 2 + x 1 x 2 x 3 + x 1 x 2 x 3 = x 1 (x 2 + x 2 )x 3 + x 1 x 2 (x 3 + x 3 ) + x 1 x 2 x 3 + x 1 x 2 x 3 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 = x 1 x 3 + (x 1 + x 1 )x 2 x 3 + (x 1 + x 1 )x 2 x 3 = x 1 x 3 + x 2 x 3 + x 2 x 3
2.12. Derivation of the minimum sum-of-products expression:
f = x 1 x 2 x 3 + x 1 x 2 x 4 + x 1 x 2 x 3 x 4 = x 1 x 2 x 3 (x 4 + x 4 ) + x 1 x 2 x 4 + x 1 x 2 x 3 x 4 = x 1 x 2 x 3 x 4 + x 1 x 2 x 3 x 4 + x 1 x 2 x 4 + x 1 x 2 x 3 x 4 = x 1 x 2 x 3 + x 1 x 2 (x 3 + x 3 )x 4 + x 1 x 2 x 4 = x 1 x 2 x 3 + x 1 x 2 x 4 + x 1 x 2 x 4
2.13. The simplest POS expression is derived as
f = (x 1 + x 3 + x 4 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 + x 4 ) = (x 1 + x 3 + x 4 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 + x 4 )(x 1 + x 2 + x 3 + x 4 ) = (x 1 + x 3 + x 4 )(x 1 + x 2 + x 3 )((x 1 + x 2 + x 4 )(x 3 + x 3 )) = (x 1 + x 3 + x 4 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 4 ) · 1 = (x 1 + x 3 + x 4 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 4 )
2.14. Derivation of the minimum product-of-sums expression:
f = (x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 ) = ((x 1 + x 2 ) + x 3 )((x 1 + x 2 ) + x 3 )(x 1 + (x 2 + x 3 ))(x 1 + (x 2 + x 3 )) = (x 1 + x 2 )(x 2 + x 3 )
2.15. (a) Location of all minterms in a 3-variable Venn diagram:
x 1 m 4 m 2
m 1
x 2
x 3
m 5 m 3
m 7
m 6
m 0
2.19. The simplest SOP implementation of the function is
f = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 = (x 1 + x 1 )x 2 x 3 + x 1 (x 2 + x 2 )x 3 = x 2 x 3 + x 1 x 3
2.20. The simplest SOP implementation of the function is
f = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 = x 1 (x 2 + x 2 )x 3 + x 1 (x 2 + x 2 )x 3 + (x 1 + x 1 )x 2 x 3 = x 1 x 3 + x 1 x 3 + x 2 x 3
Another possibility is
f = x 1 x 3 + x 1 x 3 + x 1 x 2
2.21. The simplest POS implementation of the function is
f = (x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 ) = ((x 1 + x 3 ) + x 2 )((x 1 + x 3 ) + x 2 )(x 1 + x 2 + x 3 ) = (x 1 + x 3 )(x 1 + x 2 + x 3 )
2.22. The simplest POS implementation of the function is
f = (x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 ) = ((x 1 + x 2 ) + x 3 )((x 1 + x 2 ) + x 3 )((x 1 + x 3 ) + x 2 )((x 1 + x 3 ) + x 2 ) = (x 1 + x 2 )(x 1 + x 3 )
2.23. The lowest cost circuit is defined by
f (x 1 , x 2 , x 3 ) = x 1 x 2 + x 1 x 3 + x 2 x 3
2.24. The truth table that corresponds to the timing diagram in Figure P2.3 is
x 1 x 2 x 3 f
0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0
The simplest SOP expression is f = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3.
2.25. The truth table that corresponds to the timing diagram in Figure P2.4 is
x 1 x 2 x 3 f
0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1
The simplest SOP expression is derived as follows:
f = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 = x 1 (x 2 + x 2 )x 3 + x 1 x 2 (x 3 + x 3 ) + (x 1 + x 1 )x 2 x 3 + x 1 x 2 x 3 = x 1 · 1 · x 3 + x 1 x 2 · 1 + 1 · x 2 x 3 + x 1 x 2 x 3 = x 1 x 3 + x 1 x 2 + x 2 x 3 + x 1 x 2 x 3
(b) The canonical SOP expression is
f = x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 +x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0
(c) The simplest SOP expression is
f = x 1 x 0 + y 1 y 0 + x 1 y 0 + x 0 y 1
2.28. Using the ciruit in Figure 2.25a as a starting point, the function in Figure 2.24 can be implemented using NAND gates as follows:
f
x 1 x 2 x 3
2.29. Using the ciruit in Figure 2.25b as a starting point, the function in Figure 2.24 can be implemented using NOR gates as follows:
f
x 1
x 2
x 3
2.30. The circuit in Figure 2.33 can be implemented using NAND and NOR gates as follows:
g
h
x 3
x 1
x 2 x 4 f
2.31. The minimum-cost SOP expression for the function f (x 1 , x 2 , x 3 ) =
m(3, 4 , 6 , 7) is
f = x 1 x 3 + x 2 x 3
The corresponding circuit implemented using NAND gates is
f
x 1
x 2
x 3
2.32. A minimum-cost SOP expression for the function f (x 1 , x 2 , x 3 ) =
m(1, 3 , 4 , 6 , 7) is
f = x 1 x 2 + x 1 x 3 + x 1 x 3
The corresponding circuit implemented using NAND gates is
f
x 1
x 2
x 3
2.38. The circuit in Figure 2.25b can be implemented using;
module prob2 38 (x1, x2, x3, f); input x1, x2, x3; output f;
not (notx1, x1); not (notx2, x2); not (notx3, x3); or (a, x1, x2, x3); or (b, notx1, notx2, x3); or (c, notx1, x2, notx3); or (d, x1, notx2, notx3); and (f, a, b, c, d);
endmodule
2.39. The simplest circuit is obtained in the POS form as
f = (x 1 + x 2 + x 3 )(x 1 + x 2 + x 3 )
Verilog code that implements the circuit is
module prob2 39 (x1, x2, x3, f); input x1, x2, x3; output f;
or (g, x1, x2, x3); or (h, ∼x1, ∼x2, ∼x3); and (f, g, h);
endmodule
2.40. The simplest circuit is obtained in the SOP form as
f = x 2 + x 1 x 3 + x 1 x 3
Verilog code that implements the circuit is
module prob2 40 (x1, x2, x3, f); input x1, x2, x3; output f;
assign f = ∼x2 | (∼x1 & x3) | (x1 & ∼x3);
endmodule
2.41. The Verilog code is
module prob2 41 (x1, x2, x3, x4, f1, f2); input x1, x2, x3, x4; output f1, f2;
assign f1 = (x1 & ∼x3) | (x2 & ∼x3) | (∼x3 & ∼x4) | (x1 & x2) | (x1 & ∼x4); assign f2 = (x1 | ∼x3) & (x1 | x2 | ∼x4) & (x2 | ∼x3 | ∼x4);
endmodule
2.42. The Verilog code is
module prob2 42 (x1, x2, x3, x4, f1, f2); input x1, x2, x3, x4; output f1, f2;
assign f1 = (x1 & x3) | (∼x1 & ∼x3) | (x2 & x4) | (∼x2 & ∼x4); assign f2 = (x1 & x2 & ∼x3 & ∼x4) | (∼x1 & ∼x2 & x3 & x4) | (x1 & ∼x2 & ∼x3 & x4) | (∼x1 & x2 & x3 & ∼x4);
endmodule
3.3. (a) A SOP expression for f in Figure P3.3 is:
f = (x 1 ⊕ x 2 ) ⊕ x 3 = (x 1 ⊕ x 2 )x 3 + (x 1 ⊕ x 2 )x 3 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3
which is equivalent to the expression derived in problem 3.2.
(b) Assuming the XOR gates are implemented as shown in Figure 3.61b
#transistors = XOR gates × 8 = 2 × 8 = 16
3.4. Using the circuit
The number of transistors needed is 16.
3.5. Using the circuit
The number of transistors needed is 20.
3.6. (a) x 1 x 2 x 3 f
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
(b) The canonical SOP expression is
f = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3
The number of transistors required using only AND, OR, and NOT gates is
#transistors = NOT gates × 2 + AND gates × 8 + OR gates × 12 = 3 × 2 + 5 × 8 + 1 × 12 = 58
3.7. (a) x 2 x 3 x 4 f
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
x 1
0 0 0 0 0 0 0
x 2 x 3 x 4 f
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
x 1
1 1 1 1 1 1 1
(b)
f = x 1 x 2 x 3 x 4 + x 1 x 2 x 3 x 4 + x 1 x 2 x 3 x 4 = x 1 x 3 x 4 + x 2 x 3 x 4
The number of transistors required using only AND, OR, and NOT gates is
#transistors = NOT gates × 2 + AND gates × 8 + OR gates × 4 = 4 × 2 + 2 × 8 + 1 × 4 = 28
VDD
Vx 1
Vx 2
Vx 3
V (^) f
VDD
Vx 1
Vx 3
V (^) f
Vx 4
Vx 2
VDD
V (^) y
V (^) z
V (^) f
V (^) x
VDD
VDD
V (^) y
V (^) z
V (^) y V (^) z
V (^) x
V (^) f
VDD
V (^) z V (^) y
V (^) x
V (^) y
V (^) z
3.14. (a) Since VDS ≥ VGS − VT the NMOS transistor is operating in the saturation region:
ID =
k′ n
μA V^2
× 5 × (5 V − 1 V)^2 = 800 μA
(b) In this case VDS < VGS − VT , thus the NMOS transistor is operating in the triode region:
ID = k n′
μA V^2
= 78 μA
3.15. (a) Since VDS ≤ VGS − VT the PMOS transistor is operating in the saturation region:
ID =
k p′
μA V^2
× 5 × (−5 V + 1 V)^2 = 400 μA
(b) In this case VDS > VGS − VT , thus the PMOS transistor is operating in the triode region:
ID = k′ p
μA V^2
= 39 μA
