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VHDL Image Processing Lab: Mirroring, Contrast Stretching, and Median Filtering - Prof. Ma, Lab Reports of Electrical and Electronics Engineering

A lab exercise focused on image processing algorithms using hardware description languages (vhdl) in eecc 0306-351. Students are required to implement mirroring, contrast stretching, and median filtering algorithms, practice synthesis, and test decoders using verilog hdl. Detailed instructions and examples for each algorithm, as well as requirements for input and output formats.

Typology: Lab Reports

2009/2010

Uploaded on 03/28/2010

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EECC 0306- 351: Hardware Description Language Lab
LAB#7
The objective of this lab exercise is:
1. To practice behavioral description in VHDL (using 2D arrays, reading and writing from/to files) by
implementation of some basic image processing algorithms - mirroring, contrast stretching, and me-
dian filtering.
2. To synthesize the behavioral description of the state machine from lab#5.
Practice synthesis for various coding styles of states.
3. Use Verilog HDL to construct and simulate model of a decoder from lab#2. Test it using Verilog’s
test bench with initial statement.
1)
Design and simulate (run for any time – e.g. 1 ns) behavioral architectures for the following image processing
algorithms: mirroring (vertical, horizontal), contrast stretching (to enhance the contrast of an image) and median
filtering (to reject salt and pepper noise and smoothing).
Each of the architectures is to be described with the use of 3 separate processes. The first process reads in an im-
age from a textual file, the second one performs an operation on the image and the third one writes the result to
the textual output file.
To model memories (for storing images) declare appropriate signals in your architecture (2D arrays of integers
from 0 to 255). You will need 2 such objects (signals or shared variables) – one for the original image and the
second one for the results. You will need 1D array of integers to calculate the histogram of an image (to model the
contrast stretching algorithm).
Use internal signals to enable the communication among processes !
Implementation details for an Image Processing entity
generics: inputs: outputs:
max_row : integer (read from image)
max_col : integer (read from image)
win_size : integer (3, 5)
percentagelow : integer (3, 5 %)
percentagehigh : integer (3, 5 %)
no inputs no outputs
max_row the number of rows processed image is composed of,
max_col the number of columns processed image is composed of,
win_size the size of the window for the median filter,
percentagelow the lower threshold for contrast stretching (used to calculate glow !),
percentagehigh the higher threshold for contrast stretching (used to calculate ghigh !);
The input images are in PGM format (Portable Grey Map). The PGM image format stores the image data in a tex-
tual format without any compression, as space separated integer values. The values range from 0 (darkest) to 255
(lightest). The conversion of images into PGM format can be done using of xv (x-view) program (xv allows you
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EECC 0306- 351: Hardware Description Language Lab

LAB#

The objective of this lab exercise is:

1. To practice behavioral description in VHDL (using 2D arrays, reading and writing from/to files) by implementation of some basic image processing algorithms - mirroring, contrast stretching, and me- **dian filtering.

  1. To synthesize the behavioral description of the state machine from lab#5.** **Practice synthesis for various coding styles of states.
  2. Use Verilog HDL to construct and simulate model of a decoder from lab#2. Test it using Verilog’s** test bench with initial statement.

Design and simulate (run for any time – e.g. 1 ns) behavioral architectures for the following image processing algorithms: mirroring (vertical, horizontal), contrast stretching (to enhance the contrast of an image) and median filtering (to reject salt and pepper noise and smoothing).

Each of the architectures is to be described with the use of 3 separate processes. The first process reads in an im- age from a textual file, the second one performs an operation on the image and the third one writes the result to the textual output file. To model memories (for storing images) declare appropriate signals in your architecture (2D arrays of integers from 0 to 255). You will need 2 such objects (signals or shared variables) – one for the original image and the second one for the results. You will need 1D array of integers to calculate the histogram of an image (to model the contrast stretching algorithm).

Use internal signals to enable the communication among processes!

Implementation details for an Image Processing entity

generics: inputs: outputs:

max_row : integer (read from image) max_col : integer (read from image) win_size : integer (3, 5) percentagelow : integer (3, 5 %) percentagehigh : integer (3, 5 %)

no inputs no outputs

max_row the number of rows processed image is composed of, max_col the number of columns processed image is composed of, win_size the size of the window for the median filter , percentagelow the lower threshold for contrast stretching (used to calculate glow !) , percentagehigh the higher threshold for contrast stretching (used to calculate ghigh !);

The input images are in PGM format (Portable Grey Map). The PGM image format stores the image data in a tex- tual format without any compression, as space separated integer values. The values range from 0 (darkest) to 255 (lightest). The conversion of images into PGM format can be done using of xv (x-view) program ( xv allows you

to view PGM images as well). The header of the PGM file is usually composed of 4 lines. In the 3-rd line you can find the number of columns and rows of the image.

Mirroring details:

Simply make a vertical and a horizontal reflection of the input image. This part is to practice reading and writing from/to an image file – don’t attach these results to the report.

Perform mirroring on ”Frog” test image.

Contrast stretching details:

An image of low contrast has a small difference between its dark and light pixel values. The histogram (the prob- ability of occurrence of a certain gray level) of a low contrast image is usually skewed either to the left (mostly light), to the right (mostly dark), or located around the middle (mostly gray). Contrast stretching takes an image that has a skewed contrast and stretches the histogram of the image so that the full dynamic range of the image is filled (to make better use of possible values). It requires a lower threshold and a higher threshold as inputs. The lower threshold, percentagelow (glow – corresponding border gray level) , is the percentage of pixels to be set to 0. The higher threshold, percentage- high (ghigh – corresponding border gray level) , is the percentage of pixels to be set to 255. The output value (gray level of a given pixel) is calculated according to the formula below x - the gray level of a pixel ):

0 if x <= glow

output value of a pixel = 255 * (x – glow) / (ghigh – glow) if x > glow and x < ghigh

255 if x >= ghigh

Fig. 1. Contrast stretching example - histograms before (original image) and after (processed image).

Perform contrast stretching on ”Boat” test image. Discuss results.

Median filtering details:

In median filtering, the gray level of each pixel is replaced by the median of the gray levels in the neighborhood of that pixel. In order to perform median filtering in the neighborhood of a pixel, first sort the values of the pixel and its neighbors ( in the window 3x3 and 5x5 pixels ), determine the median, and assign this value to the pixel. Perform median filtering on ”Lenna” test image (with salt and pepper noise added); discuss the results – the influence of the size of the window.

library ieee ; use ieee.std_logic_1164 .all; entity reg is port (c1, c2, a, b, c, d, e : in std_logic; dout0, dout1, dout2 : out std_logic); end entity reg; architecture cos of reg is signal tmp: std_logic; begin process (c1) begin if (c1' event and c1='1') then tmp <= a and b; dout0<= tmp; end if; end process; process (c2) variable tmp: std_logic; begin if (c2' event and c2='1') then tmp := c and d; dout1<= tmp; end if; end process; process (e, a, b) begin if e='1' then dout2<= a and b; end if ; end process; end architecture cos;

3)

Use Verilog HDL to construct and simulate model of a decoder from lab#2. Test it using Verilog’s test bench with initial statement.

Use structural, data flow and behavioral styles of the description.

Report – Part 3:

Please include the following items in the lab report:

  • Source code of structural and data flow models; simulation results – waveforms.

Questions:

  1. Synthesize and after that explain in details the synthesis results of the following VHDL code.