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ECE 337 Fall 2008 HW 5: Cache Access Times and Hit Ratios, Assignments of Computer Architecture and Organization

Information about the access times and hit ratios for different levels of cache in an electronic engineering course from fall 2008. Students are required to determine the expected access time for a given architecture and decide which cache addition would result in a better hit rate.

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Pre 2010

Uploaded on 07/22/2009

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koofers-user-rh8 🇺🇸

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ECE 337 Fall 2008
HW 5
Due Nov, 03, 2008 (Monday)
Problems on Textbook:
Exercises 10, 16, 20, 21, 23, 24, 26 in Chapter 4
Problem 8
What is the expected access time for the following architecture?
–L1 Cache: access time, 1 cycle; total hit ratio, 85%
–L2 Cache: access time, 10 cycles; total hit ratio, 95%
–L2 Cache: access time, 10 cycles; total hit ratio, 99%
–Memory: access time, 100 cycles.
Additional L1 or L2 cache could be added at the same cost. If additional L1 cache results
in a 90% hit rate and additional L2 cache results in 98% hit rate, which one would be the
better addition here?

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ECE 337 Fall 2008

HW 5

Due Nov, 03, 2008 (Monday)

Problems on Textbook:

Exercises 10, 16, 20, 21, 23, 24, 26 in Chapter 4

Problem 8 What is the expected access time for the following architecture? –L1 Cache: access time, 1 cycle; total hit ratio, 85% –L2 Cache: access time, 10 cycles; total hit ratio, 95% –L2 Cache: access time, 10 cycles; total hit ratio, 99% –Memory: access time, 100 cycles. Additional L1 or L2 cache could be added at the same cost. If additional L1 cache results in a 90% hit rate and additional L2 cache results in 98% hit rate, which one would be the better addition here?