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SN54F74 and SN74F74 D-Type Flip-Flops with Clear and Preset - Prof. Roger Doering, Study notes of Computer Science

California State University (CSU) - East Bay Computer Science

Prof. Roger Doering

Information about the dual positive-edge-triggered d-type flip-flops with clear and preset (sn54f74 and sn74f74) as detailed in the datasheet sdfs046a from texas instruments. The flip-flops contain two independent positive-edge-triggered d-type flip-flops with clear and preset inputs. The data sheet covers functional table, logic symbol, logic diagram, absolute maximum ratings, recommended operating conditions, electrical characteristics, and timing requirements.

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SN54F74, SN74F74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCTOBER 1993

Copyright  1993, Texas Instruments Incorporated

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

•Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These devices contain two independent positive-

edge-triggered D-type flip-flops. A low level at the

preset (PRE) or clear (CLR) inputs sets or resets

the outputs regardless of the levels of the other

inputs. When PRE and CLR are inactive (high),

data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a voltage level and is not

directly related to the rise time of the clock pulse.

Following the hold-time interval, data at the

D input may be changed without affecting the

levels at the outputs.

The SN54F74 is characterized for operation over

the full military temperature range of –55°C to

125°C. The SN74F74 is characterized for

operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

HLXXLH

LLXXH

†

H

†

HH↑HHL

HH↑LLH

HHLXQ

0

Q

0

†

The output levels are not guaranteed to meet the

minimum levels for VOH. Furthermore, this

configuration is nonstable; that is, it will not persist

when PRE or CLR returns to its inactive (high)

level.

SN54F74 ...J PACKAGE

SN74F74 ...D OR N PACKAGE

(TOP VIEW)

SN54F74 . . . FK PACKAGE

(TOP VIEW)

3212019

910111213

4

5

6

7

8

18

17

16

15

14

2D

NC

2CLK

NC

2PRE

1CLK

NC

1PRE

NC

1Q

1D

1CLR

NC

2Q

2Q V

2CLR

1Q

GND

NC

CC

NC – No internal connection

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1CLK

1PRE

1Q

GND

VCC

2CLR

2D

2CLK

2PRE

2Q

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCTOBER 1993

Copyright  1993, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These devices contain two independent positive-

edge-triggered D-type flip-flops. A low level at the

preset (PRE) or clear (CLR) inputs sets or resets

the outputs regardless of the levels of the other

inputs. When PRE and CLR are inactive (high),

data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a voltage level and is not

directly related to the rise time of the clock pulse.

Following the hold-time interval, data at the

D input may be changed without affecting the

levels at the outputs.

The SN54F74 is characterized for operation over

the full military temperature range of –55°C to

125 °C. The SN74F74 is characterized for

operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L

H L X X L H

L L X X H†^ H†

H H ↑ H H L

H H ↑ L L H

H H L X Q0 Q

† The output levels are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when PRE or CLR returns to its inactive (high) level.

SN54F74... J PACKAGE

SN74F74... D OR N PACKAGE

(TOP VIEW)

SN54F74... FK PACKAGE

(TOP VIEW)

2D

NC

2CLK

NC

2PRE

1CLK

NC

1PRE

NC

1Q

1D1CLRNC

2Q2Q

V 2CLR

1Q

GND

NC

CC

NC – No internal connection

1CLR

1D

1CLK

1PRE

1Q

GND

V CC

2CLR

2D

2CLK

2PRE

2Q

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCTOBER 1993

2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol†

S

1CLK

1D

R

1Q

C

2CLK

2D

2Q

1PRE

2PRE

1CLR

2CLR

1Q

2Q

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.

logic diagram, each flip-flop (positive logic)

TG

C

TG

C

TG

C

TG

C

PRE

CLK

D

CLR

Q

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡

Supply voltage range, V CC.......................................................... –0.5 V to 7 V

Input voltage range, VI (see Note 1).................................................. –1.2 V to 7 V

Input current range.............................................................. –30 mA to 5 mA

Voltage range applied to any output in the high state.................................. –0.5 V to VCC

Current into any output in the low state..................................................... 40 mA

Operating free-air temperature range: SN54F74.................................... –55°C to 125°C

SN74F74........................................ 0 °C to 70°C

Storage temperature range....................................................... –65°C to 150°C

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS046A – MARCH 1987 – REVISED OCTOBER 1993

2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics (see Note 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

CL = 50 pF, RL = 500 Ω , TA = 25 ° C

VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω , (INPUT) (OUTPUT) TA = MIN to MAX†^ UNIT ′ F74 SN54F74 SN74F MIN TYP MAX MIN MAX MIN MAX fmax 100 145 80 100 MHz tPLH CLK (^) Q or Q

ns tPHL

CLK (^) Q or Q 3.6 5.8 8 4.4 10.5 3.6 9.

ns

tPLH PRE or CLR Q or Q

ns tPHL

PRE or CLR Q or Q 2.7 6.6 9 3.5 11.5 2.7 10.

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1.