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UNIT - 2
Instruction Formats (Zero, One, Two and Three
Address Instruction)
Computer perform task on the basis of instruction provided. A instruction in computer comprises of groups called fields. These field contains different information as for computers every thing is in 0 and 1 so each field has different significance on the basis of which a CPU decide what so perform. The most common fields are:
Operation field which specifies the operation to be performed like addition. Address field which contain the location of operand, i.e., register or memory location. Mode field which specifies how operand is to be founded. A instruction is of various length depending upon the number of addresses it contain. Generally CPU organization are of three types on the basis of number of address fields:
- Single Accumulator organization
- General register organization
- Stack organization In first organization operation is done involving a special register called accumulator. In second on multiple registers are used for the computation purpose. In third organization the work on stack basis operation due to which it does not contain any address field. It is not necessary that only a single organization is applied a blend of various organization is mostly what we see generally.
On the basis of number of address instruction are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.
- Zero Address Instructions –
A stack based computer do not use address field in instruction.To evaluate a expression first it is converted to revere Polish Notation i.e. Post fix Notation.
Expression: X = (A+B)(C+D) Postfixed : X = AB+CD+ TOP means top of stack M[X] is any memory location
PUSH A TOP = A
PUSH B TOP = B
ADD TOP = A+B
PUSH C TOP = C
PUSH D TOP = D
ADD TOP = C+D
MUL TOP = (C+D)*(A+B)
POP X M[X] = TOP
- One Address Instructions – This use a implied ACCUMULATOR register for data manipulation.One operand is in accumulator and other is in register or memory location.Implied means that the CPU already know that one operand is in accumulator so there is no need to specify it.
Expression: X = (A+B)*(C+D) AC is accumulator M[] is any memory location M[T] is temporary location
ADD R2, D R2 = R2 + D
MUL R1, R2 R1 = R1 * R
MOV X, R1 M[X] = R
- Three Address Instructions – This has three address field to specify a register or a memory location. Program created are much short in size but number of bits per instruction increase. These instructions make creation of program much easier but it does not mean that program will run much faster because now instruction only contain more information but each micro operation (changing content of register, loading address in address bus etc.) will be performed in one cycle only.
Expression: X = (A+B)*(C+D) R1, R2 are registers M[] is any memory location
Computer Organization | Different Instruction Cycles
Registers Involved In Each Instruction Cycle:
Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies the address in memory for a read or write operation. Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the value to be stored in memory or the last value read from the memory. Program Counter(PC) : Holds the address of the next instruction to be fetched. Instruction Register(IR) : Holds the last instruction fetched. The Instruction Cycle – Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro- operations. In the above examples, there is one sequence each for the Fetch, Indirect, Execute and Interrupt Cycles.
The Indirect Cycle is always followed by the Execute Cycle. The Interrupt Cycle is always followed by the Fetch Cycle. For both fetch and execute cycles, the next cycle depends on the state of the system.
Step 1: The address in the program counter is moved to the memory address register(MAR), as this is the only register which is connected to address lines of the system bus.
Step 2: The address in MAR is placed on the address bus, now the control unit issues a READ command on the control bus, and the result appears on the data bus and is then copied into the memory buffer register(MBR). Program counter is incremented by one, to get ready for the next instruction.(These two action can be performed simultaneously to save time)
Step 3: The content of the MBR is moved to the instruction register(IR).
Thus, a simple Fetch Cycle consist of three steps and four micro-operation. Symbolically, we can write these sequence of events as follows:-
Step 1: The address field of the instruction is transferred to the MAR. This is used to fetch the address of the operand. Step 2: The address field of the IR is updated from the MBR.(So that it now contains a direct addressing rather than indirect addressing) Step 3: The IR is now in the state, as if indirect addressing has not been occurred. Note: Now IR is ready for the execute cycle, but it skips that cycle for a moment to consider the Interrupt Cycle.
- The Execute Cycle The other three cycles( Fetch, Indirect and Interrupt ) are simple and predictable. Each of them requires simple, small and fixed sequence of micro-operation. In each case same micro-operation are repeated each time around. Execute Cycle is different from them. Like, for a machine with N different opcodes there are N different sequence of micro-operations that can occur. Lets take an hypothetical example :- consider an add instruction:
Here, this instruction adds the content of location X to register R. Corresponding micro-operation will be:-
We begin with the IR containing the ADD instruction. Step 1: The address portion of IR is loaded into the MAR. Step 2: The address field of the IR is updated from the MBR, so the reference
memory location is read. Step 3: Now, the contents of R and MBR are added by the ALU. Lets take a complex example :-
Here, the content of location X is incremented by 1. If the result is 0, the next instruction will be skipped. Corresponding sequence of micro-operation will be :-
Here, the PC is incremented if (MBR) = 0. This test (is MBR equal to zero or not) and action (PC is incremented by 1) can be implemented as one micro-operation. Note : This test and action micro-operation can be performed during the same time unit during which the updated value MBR is stored back to memory.
- The Interrupt Cycle : At the completion of the Execute Cycle, a test is made to determine whether any enabled interrupt has occurred or not. If an enabled interrupt has occurred then Interrupt Cycle occurs. The natare of this cycle varies greatly from one machine to another. Lets take a sequence of micro-operation:-
Comparison between Horizontal micro-programmed control unit and Vertical micro- programmed control unit:
HORIZONTAL Μ-PROGRAMMED CU VERTICAL Μ-PROGRAMMED CU
It supports longer control word. It supports shorter control word.
It allows higher degree of parallelism.
If degree is n, then n Control Signals
are enabled at a time.
It allows low degree of parallelism i.e., degree of
parallelism is either 0 or 1.
No additional hardware is required.
Additional hardware in the form of decoders are
required to generate control signals.
It is faster than Vertical micro-
programmed control unit.
it is slower than Horizontal micro-programmed
control unit.
It is less flexible than Vertical micro-
programmed control unit.
It is more flexible than Horizontal micro-
programmed control unit.
Horizontal micro-programmed control
unit uses horizontal microinstruction,
where every bit in the control field
attaches to a control line.
Vertical micro-programmed control unit uses
vertical microinstruction, where a code is used
for each action to be performedand thedecoder
translates this code into individual control
HORIZONTAL Μ-PROGRAMMED CU VERTICAL Μ-PROGRAMMED CU
signals.
Horizontal micro-programmed control
unit makes less use of ROM encoding
than vertical micro-programmed
control unit.
Vertical micro-programmed control unit makes
more use of ROM encoding to reduce the length
of the control word.
Example: Consider a hypothetical Control Unit which supports 4 k words. The Hardware contains 64 control signals and 16 Flags. What is the size of control word used in bits and control memory in byte using: a) Horizontal Programming b) Vertical programming Solution:
a)For Horizontal
64 bits for 64 signals
Control Word Size = 4 + 64 + 12 = 80 bits
Control Memory = 4 kW = ( (4* 80) / 8 ) = 40 kByte
Functions of the Control Unit –
- It coordinates the sequence of data movements into, out of, and between a processor’s many sub-units.
- It interprets instructions.
- It controls data flow inside the processor.
- It receives external instructions or commands to which it converts to sequence of control signals.
- It controls many execution units(i.e. ALU, data buffers and registers) contained within a CPU.
- It also handles multiple tasks, such as fetching, decoding, execution handling and storing results. Types of Control Unit – There are two types of control units: Hardwired control unit and Microprogrammable control unit.
- Hardwired Control Unit – In the Hardwired control unit, the control signals that are important for instruction execution control are generated by specially designed hardware logical circuits, in which we can not modify the signal generation method without physical change of the circuit structure. The operation code of an instruction contains the basic data for control signal generation. In the instruction decoder, the operation code is decoded. The instruction decoder constitutes a set of many decoders that decode different fields of the instruction opcode. As a result, few output lines going out from the instruction decoder obtains active signal values. These output lines are connected to the inputs of the matrix that generates control signals for executive units of the computer. This matrix implements logical combinations of the decoded signals from the instruction opcode with the outputs from the matrix that generates signals representing consecutive control unit states and with signals coming from the outside of the processor, e.g. interrupt signals. The matrices are built in a similar way as a programmable logic arrays.
Control signals for an instruction execution have to be generated not in a single time point but during the entire time interval that corresponds to the instruction execution cycle. Following the structure of this cycle, the suitable sequence of internal states is organized in the control unit.
A number of signals generated by the control signal generator matrix are sent back to inputs of the next control state generator matrix. This matrix combines these signals with the timing signals, which are generated by the timing unit based on the rectangular patterns usually supplied by the quartz generator. When a new instruction arrives at the control unit, the control units is in the initial state of new instruction fetching. Instruction decoding allows the control unit enters the first state relating execution of the new instruction, which lasts as long as the timing signals and other input signals as flags and state information of the computer remain unaltered. A change of any of the earlier mentioned signals stimulates the change of the control unit state.
This causes that a new respective input is generated for the control signal generator matrix. When an external signal appears, (e.g. an interrupt) the control unit takes entry into a next control state that is the state concerned with the reaction to this external signal (e.g. interrupt processing). The values of flags and state variables of the computer are used to select suitable states for the instruction execution cycle.
The last states in the cycle are control states that commence fetching the next instruction of the program: sending the program counter content to the main memory address buffer register and next, reading the instruction word to the instruction register of computer. When the ongoing instruction is the stop instruction that ends program execution, the control unit enters an operating system state, in which it waits for a next user directive.
instruction of the given microprogram is the microinstruction that fetches the next instruction from the main memory to the instruction register.
With a two-level control store: In this, in a control unit with a two-level control store, besides the control memory for microinstructions, a nano-instruction memory is included. In such a control unit, microinstructions do not contain encoded control signals. The operation part of microinstructions contains the address of the word in the nano-instruction memory, which contains encoded control signals. The nano-instruction memory contains all combinations of control signals that appear in microprograms that interpret the complete instruction set of a given computer, written once in the form of nano- instructions.
In this way, unnecessary storing of the same operation parts of microinstructions is avoided. In this case, microinstruction word can be much shorter than with the single level control store. It gives a much smaller size in bits of the microinstruction memory and, as a result, a much smaller size of the entire control memory. The microinstruction memory contains the control for selection of consecutive microinstructions, while those control signals are generated at the basis of nano-instructions. In nano-instructions, control signals are frequently encoded using 1 bit/ 1 signal method that eliminates decoding.
Memory Hierarchy Design and its Characteristics
In the Computer System Design, Memory Hierarchy is an enhancement to organize the memory such that it can minimize the access time. The Memory Hierarchy was developed based on a program behavior known as locality of references.The figure below clearly demonstrates the different levels of memory hierarchy :
This Memory Hierarchy Design is divided into 2 main types:
- External Memory or Secondary Memory – Comprising of Magnetic Disk, Optical Disk, Magnetic Tape i.e. peripheral storage devices which are accessible by the processor via I/O Module.
- Internal Memory or Primary Memory – Comprising of Main Memory, Cache Memory & CPU registers. This is directly accessible by the processor. We can infer the following characteristics of Memory Hierarchy Design from above figure:
- Capacity: It is the global volume of information the memory can store. As we move from top to bottom in the Hierarchy, the capacity increases.
- Access Time: It is the time interval between the read/write request and the availability of the data. As we move from top to bottom in the Hierarchy, the access time increases.
