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Introduction to 8085 microprocessor, Cheat Sheet of Microprocessors

Thos is the diagram for microprocessor and the description with provided pin diagram and block diagram

Typology: Cheat Sheet

2023/2024

Uploaded on 02/18/2025

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8259 Programmable Interrupt Controller (PIC)
Intel 8259 is aProgrammable Interrupt Controller (PIC). There are 5
hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086
microprocessors respectively. But by connecting Intel 8259 with these
microprocessors, we can increase their interrupt handling capability. Intel
8259 combines the multi-interrupt input sources into a single interrupt output.
Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For
example, Interfacing of 8085 and 8259 increases the interrupt handling
capability of 8085 microprocessor from 5 to 8 interrupt levels.
Features of Intel 8259 PIC are as follows:
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered
interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by
cascading further 8259 PICs.
5. Clock cycle is not required.
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8259 Programmable Interrupt Controller (PIC) Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5 hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086 microprocessors respectively. But by connecting Intel 8259 with these microprocessors, we can increase their interrupt handling capability. Intel 8259 combines the multi-interrupt input sources into a single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7. For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessor from 5 to 8 interrupt levels. Features of Intel 8259 PIC are as follows:

  1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
  2. It can be programmed either in level triggered or in edge triggered interrupt level.
  3. We can mask individual bits of interrupt request register.
  4. We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259 PICs.
  5. Clock cycle is not required.

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.

  1. Data bus buffer – This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to the control logic of 8259 microprocessor. After selection of Interrupt by 8259 microprocessor (based on priority of the interrupt), it transfer the opcode of the selected Interrupt and address of the Interrupt service sub routine to the other connected microprocessor. The data bus buffer consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data can be transferred at a time.
  2. Read/Write logic – This block works only when the value of pin CS is low (as this pin is active low). This block is responsible for the flow of data depending upon the inputs of RD and WR. These two pins are active low pins used for read and write operations.
  3. Control logic – It is the center of the PIC and controls the functioning of every block. It has pin INTR which is connected with other microprocessor for taking interrupt request and pin INT for giving the output. If 8259 is enabled, and the other microprocessor Interrupt flag is high then this causes the value of the output INT pin high and in this way 8259 responds to the request made by other microprocessor.