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Revision 2.
June 8, 2003
MIPS Technologies, Inc.
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MIPS32™ Architecture For Programmers
Volume I: Introduction to the MIPS32™
Architecture
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MIPS32™ Architecture For Programmers Volume I, Revision 2.
Template: B1.08, Built with tags: 2B ARCH MIPS
MIPS32™ Architecture For Programmers Volume I, Revision 2.00 iii
- Chapter 1 About This Book .................................................................................................................................................. Table of Contents
- 1.1 Typographical Conventions ....................................................................................................................................
- 1.1.1 Italic Text ......................................................................................................................................................
- 1.1.2 Bold Text ......................................................................................................................................................
- 1.1.3 Courier Text ..................................................................................................................................................
- 1.2 UNPREDICTABLE and UNDEFINED .................................................................................................................
- 1.2.1 UNPREDICTABLE ......................................................................................................................................
- 1.2.2 UNDEFINED ................................................................................................................................................
- 1.3 Special Symbols in Pseudocode Notation ...............................................................................................................
- 1.4 For More Information .............................................................................................................................................
- Chapter 2 The MIPS Architecture: An Introduction .............................................................................................................
- 2.1 MIPS32 and MIPS64 Overview .............................................................................................................................
- 2.1.1 Historical Perspective ...................................................................................................................................
- 2.1.2 Architectural Evolution .................................................................................................................................
- 2.1.3 Architectural Changes Relative to the MIPS I through MIPS V Architectures ...........................................
- 2.2 Compliance and Subsetting .....................................................................................................................................
- 2.3 Components of the MIPS Architecture .................................................................................................................
- 2.3.1 MIPS Instruction Set Architecture (ISA) ....................................................................................................
- 2.3.2 MIPS Privileged Resource Architecture (PRA) .........................................................................................
- 2.3.3 MIPS Application Specific Extensions (ASEs) ..........................................................................................
- 2.3.4 MIPS User Defined Instructions (UDIs) .....................................................................................................
- 2.4 Architecture Versus Implementation ....................................................................................................................
- 2.5 Relationship between the MIPS32 and MIPS64 Architectures ............................................................................
- 2.6 Instructions, Sorted by ISA ...................................................................................................................................
- 2.6.1 List of MIPS32 Instructions ........................................................................................................................
- 2.6.2 List of MIPS64 Instructions ........................................................................................................................
- 2.7 Pipeline Architecture .............................................................................................................................................
- 2.7.1 Pipeline Stages and Execution Rates ..........................................................................................................
- 2.7.2 Parallel Pipeline ..........................................................................................................................................
- 2.7.3 Superpipeline ..............................................................................................................................................
- 2.7.4 Superscalar Pipeline ....................................................................................................................................
- 2.8 Load/Store Architecture ........................................................................................................................................
- 2.9 Programming Model .............................................................................................................................................
- 2.9.1 CPU Data Formats ......................................................................................................................................
- 2.9.2 FPU Data Formats .......................................................................................................................................
- 2.9.3 Coprocessors (CP0-CP3) ............................................................................................................................
- 2.9.4 CPU Registers .............................................................................................................................................
- 2.9.5 FPU Registers .............................................................................................................................................
- 2.9.6 Byte Ordering and Endianness ...................................................................................................................
- 2.9.7 Memory Access Types ................................................................................................................................
- 2.9.8 Implementation-Specific Access Types ......................................................................................................
- 2.9.9 Cache Coherence Algorithms and Access Types .......................................................................................
- 2.9.10 Mixing Access Types ................................................................................................................................
- Chapter 3 Application Specific Extensions .........................................................................................................................
- 3.1 Description of ASEs ..............................................................................................................................................
- 3.2 List of Application Specific Instructions ..............................................................................................................
- 3.2.1 The MIPS16e Application Specific Extension to the MIPS32Architecture ...............................................
- 3.2.2 The MDMX Application Specific Extension to the MIPS64 Architecture ................................................
- 3.2.3 The MIPS-3D Application Specific Extension to the MIPS64 Architecture .............................................
- ii MIPS32™ Architecture For Programmers Volume I, Revision 2. - 3.2.4 The SmartMIPS Application Specific Extension to the MIPS32 Architecture ..........................................
- Chapter 4 Overview of the CPU Instruction Set .................................................................................................................
- 4.1 CPU Instructions, Grouped By Function ..............................................................................................................
- 4.1.1 CPU Load and Store Instructions ...............................................................................................................
- 4.1.2 Computational Instructions .........................................................................................................................
- 4.1.3 Jump and Branch Instructions .....................................................................................................................
- 4.1.4 Miscellaneous Instructions ..........................................................................................................................
- 4.1.5 Coprocessor Instructions .............................................................................................................................
- 4.2 CPU Instruction Formats ......................................................................................................................................
- Chapter 5 Overview of the FPU Instruction Set .................................................................................................................
- 5.1 Binary Compatibility .............................................................................................................................................
- 5.2 Enabling the Floating Point Coprocessor ..............................................................................................................
- 5.3 IEEE Standard 754 ................................................................................................................................................
- 5.4 FPU Data Types ....................................................................................................................................................
- 5.4.1 Floating Point Formats ................................................................................................................................
- 5.4.2 Fixed Point Formats ....................................................................................................................................
- 5.5 Floating Point Register Types ...............................................................................................................................
- 5.5.1 FPU Register Models ..................................................................................................................................
- 5.5.2 Binary Data Transfers (32-Bit and 64-Bit) .................................................................................................
- 5.5.3 FPRs and Formatted Operand Layout .........................................................................................................
- 5.6 Floating Point Control Registers (FCRs) ..............................................................................................................
- 5.6.1 Floating Point Implementation Register (FIR, CP1 Control Register 0) ....................................................
- 5.6.2 Floating Point Control and Status Register (FCSR, CP1 Control Register 31) ..........................................
- 5.6.3 Floating Point Condition Codes Register (FCCR, CP1 Control Register 25) ............................................
- 5.6.4 Floating Point Exceptions Register (FEXR, CP1 Control Register 26) .....................................................
- 5.6.5 Floating Point Enables Register (FENR, CP1 Control Register 28) ..........................................................
- 5.7 Formats of Values Used in FP Registers ..............................................................................................................
- 5.8 FPU Exceptions .....................................................................................................................................................
- 5.8.1 Exception Conditions ..................................................................................................................................
- 5.9 FPU Instructions ...................................................................................................................................................
- 5.9.1 Data Transfer Instructions ...........................................................................................................................
- 5.9.2 Arithmetic Instructions ...............................................................................................................................
- 5.9.3 Conversion Instructions ..............................................................................................................................
- 5.9.4 Formatted Operand-Value Move Instructions ............................................................................................
- 5.9.5 Conditional Branch Instructions .................................................................................................................
- 5.9.6 Miscellaneous Instructions ..........................................................................................................................
- 5.10 Valid Operands for FPU Instructions ..................................................................................................................
- 5.11 FPU Instruction Formats .....................................................................................................................................
- 5.11.1 Implementation Note ................................................................................................................................
- Appendix A Instruction Bit Encodings ...............................................................................................................................
- A.1 Instruction Encodings and Instruction Classes .....................................................................................................
- A.2 Instruction Bit Encoding Tables ............................................................................................................................
- A.3 Floating Point Unit Instruction Format Encodings ...............................................................................................
- Appendix B Revision History .............................................................................................................................................
- Figure 2-1: Relationship between the MIPS32 and MIPS64 Architectures....................................................................... List of Figures
- Figure 2-2: One-Deep Single-Completion Instruction Pipeline .........................................................................................
- Figure 2-3: Four-Deep Single-Completion Pipeline ..........................................................................................................
- Figure 2-4: Four-Deep Superpipeline.................................................................................................................................
- Figure 2-5: Four-Way Superscalar Pipeline .......................................................................................................................
- Figure 2-6: CPU Registers..................................................................................................................................................
- Figure 2-7: FPU Registers for a 32-bit FPU.......................................................................................................................
- Figure 2-8: FPU Registers for a 64-bit FPU if Status FR is 1..............................................................................................
- Figure 2-9: FPU Registers for a 64-bit FPU if StatusFR is 0..............................................................................................
- Figure 2-10: Big-Endian Byte Ordering.............................................................................................................................
- Figure 2-11: Little-Endian Byte Ordering ..........................................................................................................................
- Figure 2-12: Big-Endian Data in Doubleword Format.......................................................................................................
- Figure 2-13: Little-Endian Data in Doubleword Format....................................................................................................
- Figure 2-14: Big-Endian Misaligned Word Addressing ....................................................................................................
- Figure 2-15: Little-Endian Misaligned Word Addressing..................................................................................................
- Figure 3-1: MIPS ISAs and ASEs ......................................................................................................................................
- Figure 3-2: User-Mode MIPS ISAs and Optional ASEs....................................................................................................
- Figure 4-1: Immediate (I-Type) CPU Instruction Format ..................................................................................................
- Figure 4-2: Jump (J-Type) CPU Instruction Format ..........................................................................................................
- Figure 4-3: Register (R-Type) CPU Instruction Format ....................................................................................................
- Figure 5-1: Single-Precisions Floating Point Format (S) ...................................................................................................
- Figure 5-2: Double-Precisions Floating Point Format (D).................................................................................................
- Figure 5-3: Paired Single Floating Point Format (PS) .......................................................................................................
- Figure 5-4: Word Fixed Point Format (W).........................................................................................................................
- Figure 5-5: Longword Fixed Point Format (L) ..................................................................................................................
- Figure 5-6: FPU Word Load and Move-to Operations ......................................................................................................
- Figure 5-7: FPU Doubleword Load and Move-to Operations............................................................................................
- Figure 5-8: Single Floating Point or Word Fixed Point Operand in an FPR .....................................................................
- Figure 5-9: Double Floating Point or Longword Fixed Point Operand in an FPR ............................................................
- Figure 5-10: Paired-Single Floating Point Operand in an FPR ..........................................................................................
- Figure 5-11: FIR Register Format ......................................................................................................................................
- Figure 5-12: FCSR Register Format...................................................................................................................................
- Figure 5-13: FCCR Register Format ..................................................................................................................................
- Figure 5-14: FEXR Register Format ..................................................................................................................................
- Figure 5-15: FENR Register Format ..................................................................................................................................
- Figure 5-16: Effect of FPU Operations on the Format of Values Held in FPRs................................................................
- Figure 5-17: I-Type (Immediate) FPU Instruction Format ................................................................................................
- Figure 5-18: R-Type (Register) FPU Instruction Format...................................................................................................
- Figure 5-19: Register-Immediate FPU Instruction Format ................................................................................................
- Figure 5-20: Condition Code, Immediate FPU Instruction Format ...................................................................................
- Figure 5-21: Formatted FPU Compare Instruction Format ................................................................................................
- Figure 5-22: FP RegisterMove, Conditional Instruction Format .......................................................................................
- Figure 5-23: Four-Register Formatted Arithmetic FPU Instruction Format ......................................................................
- Figure 5-24: Register Index FPU Instruction Format.........................................................................................................
- Figure 5-25: Register Index Hint FPU Instruction Format ................................................................................................
- Figure 5-26: Condition Code, Register Integer FPU Instruction Format ...........................................................................
- Figure A-1: Sample Bit Encoding Table ............................................................................................................................
- iv MIPS32™ Architecture For Programmers Volume I, Revision 2.
- Table 1-1: Symbols Used in Instruction Operation Statements ........................................................................................... List ofTables
- Table 2-1: MIPS32 Instructions .........................................................................................................................................
- Table 2-2: MIPS64 Instructions .........................................................................................................................................
- Table 2-3: Unaligned Load and Store Instructions.............................................................................................................
- Table 4-1: Load and Store Operations Using Register + Offset Addressing Mode ...........................................................
- Table 4-2: Aligned CPU Load/Store Instructions .............................................................................................................
- Table 4-3: Unaligned CPU Load and Store Instructions ...................................................................................................
- Table 4-4: Atomic Update CPU Load and Store Instructions ............................................................................................
- Table 4-5: Coprocessor Load and Store Instructions .........................................................................................................
- Table 4-6: FPU Load and Store Instructions Using Register + Register Addressing .......................................................
- Table 4-7: ALU Instructions With an Immediate Operand ...............................................................................................
- Table 4-8: Three-Operand ALU Instructions ....................................................................................................................
- Table 4-9: Two-Operand ALU Instructions ......................................................................................................................
- Table 4-10: Shift Instructions ............................................................................................................................................
- Table 4-11: Multiply/Divide Instructions ..........................................................................................................................
- Table 4-12: Unconditional Jump Within a 256 Megabyte Region.....................................................................................
- Table 4-13: PC-Relative Conditional Branch Instructions Comparing Two Registers .....................................................
- Table 4-14: PC-Relative Conditional Branch Instructions Comparing With Zero ...........................................................
- Table 4-15: Deprecated Branch Likely Instructions ..........................................................................................................
- Table 4-16: Serialization Instruction ..................................................................................................................................
- Table 4-17: System Call and Breakpoint Instructions........................................................................................................
- Table 4-18: Trap-on-Condition Instructions Comparing Two Registers ...........................................................................
- Table 4-19: Trap-on-Condition Instructions Comparing an Immediate Value ..................................................................
- Table 4-20: CPU Conditional Move Instructions...............................................................................................................
- Table 4-21: Prefetch Instructions .......................................................................................................................................
- Table 4-22: NOP Instructions.............................................................................................................................................
- Table 4-23: Coprocessor Definition and Use in the MIPS Architecture............................................................................
- Table 4-24: CPU Instruction Format Fields .......................................................................................................................
- Table 5-1: Parameters of Floating Point Data Types .........................................................................................................
- Table 5-2: Value of Single or Double Floating Point DataType Encoding .......................................................................
- Table 5-3: Value Supplied When a New Quiet NaN Is Created ........................................................................................
- Table 5-4: FIR Register Field Descriptions........................................................................................................................
- Table 5-5: FCSR Register Field Descriptions ....................................................................................................................
- Table 5-6: Cause, Enable, and Flag Bit Definitions ...........................................................................................................
- Table 5-7: Rounding Mode Definitions .............................................................................................................................
- Table 5-8: FCCR Register Field Descriptions....................................................................................................................
- Table 5-9: FEXR Register Field Descriptions....................................................................................................................
- Table 5-10: FENR Register Field Descriptions..................................................................................................................
- Table 5-11: Default Result for IEEE Exceptions Not Trapped Precisely .........................................................................
- Table 5-12: FPU Data Transfer Instructions ......................................................................................................................
- Table 5-13: FPU Loads and Stores Using Register+Offset Address Mode .......................................................................
- Table 5-14: FPU Loads and Using Register+Register Address Mode...............................................................................
- Table 5-15: FPU Move To and From Instructions .............................................................................................................
- Table 5-16: FPU IEEE Arithmetic Operations...................................................................................................................
- Table 5-17: FPU-Approximate Arithmetic Operations ......................................................................................................
- Table 5-18: FPU Multiply-Accumulate Arithmetic Operations.........................................................................................
- Table 5-19: FPU Conversion Operations Using the FCSR Rounding Mode .....................................................................
- Table 5-20: FPU Conversion Operations Using a Directed Rounding Mode ....................................................................
- Table 5-21: FPU Formatted Operand Move Instructions...................................................................................................
- Table 5-22: FPU Conditional Move on True/False Instructions ........................................................................................
- Table 5-23: FPU Conditional Move on Zero/Nonzero Instructions................................................................................... MIPS32™ Architecture For Programmers Volume I, Revision 2.00 v
- Table 5-24: FPU Conditional Branch Instructions .............................................................................................................
- Table 5-25: Deprecated FPU Conditional Branch Likely Instructions ..............................................................................
- Table 5-26: CPU Conditional Move on FPU True/False Instructions ...............................................................................
- Table 5-27: FPU Operand Format Field (fmt, fmt3) Encoding .........................................................................................
- Table 5-28: Valid Formats for FPU Operations ................................................................................................................
- Table 5-29: FPU Instruction Format Fields .......................................................................................................................
- Table A-1: Symbols Used in the Instruction Encoding Tables ..........................................................................................
- Table A-2: MIPS32 Encoding of the Opcode Field ...........................................................................................................
- Table A-3: MIPS32 SPECIAL Opcode Encoding of Function Field.................................................................................
- Table A-4: MIPS32 REGIMM Encoding of rt Field..........................................................................................................
- Table A-5: MIPS32 SPECIAL2 Encoding of Function Field ............................................................................................
- Table A-6: MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture.......................................
- Table A-7: MIPS32 MOVCI Encoding of tf Bit ................................................................................................................
- Table A-8: MIPS32 SRL Encoding of Shift/Rotate ...........................................................................................................
- Table A-9: MIPS32 SRLV Encoding of Shift/Rotate ........................................................................................................
- Table A-10: MIPS32 BSHFL Encoding of sa Field...........................................................................................................
- Table A-11: MIPS32 COP0 Encoding of rs Field..............................................................................................................
- Table A-12: MIPS32 COP0 Encoding of Function Field When rs=CO ............................................................................
- Table A-13: MIPS32 COP1 Encoding of rs Field..............................................................................................................
- Table A-14: MIPS32 COP1 Encoding of Function Field When rs=S................................................................................
- Table A-15: MIPS32 COP1 Encoding of Function Field When rs=D...............................................................................
- Table A-16: MIPS32 COP1 Encoding of Function Field When rs=W or L ......................................................................
- Table A-17: MIPS64 COP1 Encoding of Function Field When rs=PS .............................................................................
- Table A-18: MIPS32 COP1 Encoding of tf Bit When rs=S, D, or PS, Function=MOVCF ..............................................
- Table A-19: MIPS32 COP2 Encoding of rs Field..............................................................................................................
- Table A-20: MIPS64 COP1X Encoding of Function Field................................................................................................
- Table A-21: Floating Point Unit Instruction Format Encodings ........................................................................................
- vi MIPS32™ Architecture For Programmers Volume I, Revision 2.
iv MIPS32™ Architecture For Programmers Volume I, Revision 2.
Chapter 1 About This Book
1.2 UNPREDICTABLE and UNDEFINED
The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of the processor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register). Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged and unprivileged software can cause UNPREDICTABLE results or operations.
1.2.1 UNPREDICTABLE
UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. Software can never depend on results that are UNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is generated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions.
UNPREDICTABLE results or operations have several implementation restrictions:
- Implementations of operations generating UNPREDICTABLE results must not depend on any data source (memory or internal state) which is inaccessible in the current processor mode
- UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in user mode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process
- UNPREDICTABLE operations must not halt or hang the processor
1.2.2 UNDEFINED
UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction to instruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED operations or behavior may cause data loss.
UNDEFINED operations or behavior has one implementation restriction:
- UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from which there is no exit other than powering down the processor). The assertion of any of the reset signals must restore the processor to an operational state
1.3 Special Symbols in Pseudocode Notation
In this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1-1.
Table 1-1 Symbols Used in Instruction Operation Statements
Symbol Meaning
← Assignment
=, ≠ Tests for equality and inequality
|| Bit string concatenation
x y^ A y -bit string formed by y copies of the single-bit value x
1.3 Special Symbols in Pseudocode Notation ...............................................................................................................
vi MIPS32™ Architecture For Programmers Volume I, Revision 2.
b#n
A constant value n in base b. For instance 10#100 represents the decimal value 100, 2#100 represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the "b#" prefix is omitted, the default base is 10.
xy..z Selection of bits z , this expression is an empty (zero length) bit string.^ y^ through^ z^ of bit string^ x. Little-endian bit notation (rightmost bit is 0) is used. If^ y^ is less than
+, − 2’s complement or floating point arithmetic: addition, subtraction
∗, × 2’s complement or floating point multiplication (both used for either)
div 2’s complement integer division
mod 2’s complement modulo
/ Floating point division
< 2’s complement less-than comparison
2’s complement greater-than comparison
≤ 2’s complement less-than or equal comparison
≥ 2’s complement greater-than or equal comparison
nor Bitwise logical NOR
xor Bitwise logical XOR
and Bitwise logical AND
or Bitwise logical OR
GPRLEN The length in bits (32 or 64) of the CPU general-purpose registers
GPR[x] CPU general-purpose register x. The content of GPR[0] is always zero.
SGPR[s,x] In Release 2 of the Architecture, multiple copies of the CPU general-purpose registers may be implemented. SGPR[s,x] refers to GPR set s , register x. GPR[x] is a short-hand notation for SGPR[ SRSCtl CSS, x].
5.5 Floating Point Register Types ...............................................................................................................................
FCC[CC] Floating Point condition code CC. FCC[0] has the same value as COC[1].
FPR[x] Floating Point (Coprocessor unit 1), general register x
CPR[z,x,s] Coprocessor unit z , general register x, select s
CP2CPR[x] Coprocessor unit 2, general register x
CCR[z,x] Coprocessor unit z , control register x
CP2CCR[x] Coprocessor unit 2, control register x
COC[z] Coprocessor unit z condition signal
Xlat[x] Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number
BigEndianMem
Endian mode as configured at chip reset (0 →Little-Endian, 1 → Big-Endian). Specifies the endianness of the memory interface (see LoadMemory and StoreMemory pseudocode function descriptions), and the endianness of Kernel and Supervisor mode execution.
BigEndianCPU
The endianness for load and store instructions (0 → Little-Endian, 1 → Big-Endian). In User mode, this endianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be computed as (BigEndianMem XOR ReverseEndian).
Table 1-1 Symbols Used in Instruction Operation Statements
Symbol Meaning
1.4 For More Information .............................................................................................................................................
MIPS32™ Architecture For Programmers Volume I, Revision 2.00 5
Comments or questions on the MIPS32™ Architecture or this document should be directed to
Director of MIPS Architecture MIPS Technologies, Inc. 1225 Charleston Road Mountain View, CA 94043
or via E-mail to architecture@mips.com.
6 MIPS32™ Architecture For Programmers Volume I, Revision 2.
Chapter 1 About This Book
8 MIPS32™ Architecture For Programmers Volume I, Revision 2.
Chapter 2 The MIPS Architecture: An Introduction .............................................................................................................
- maintain architectural scalability
- are standardized to prevent fragmentation
- are a superset of the existing architecture
The MIPS Architecture community constantly evaluates suggestions for architectural changes and enhancements against these criteria. New releases of the architecture, while infrequent, are made at appropriate points, following these criteria. At present, there are two releases of the MIPS Architecture: Release 1 (the original version of the MIPS32 Architecture) and Release 2 which was added in 2002.
2.1.2.1 Release 2 of the MIPS32 Architecture
Enhancements included in Release 2 of the MIPS32 Architecture are:
- Vectored interrupts: This enhancement provides the ability to vector interrupts directly to a handler for that interrupt. Vectored interrupts are an option in Release 2 implementations and the presence of that option is denoted by the Config3VInt bit.
- Support for an external interrupt controller: This enhancement reconfigures the on-core interrupt logic to take full advantage of an external interrupt controller. This support is an option in Release 2 implementations and the presence of that option is denoted by the Config3 (^) EIC bit.
- Programmable exception vector base: This enhancement allows the base address of the exception vectors to be moved for exceptions that occur when StatusBEV is 0. Doing so allows multi-processor systems to have separate exception vectors for each processor, and allows any system to place the exception vectors in memory that is appropriate to the system environment. This enhancement is required in a Release 2 implementation.
- Atomic interrupt enable/disable: Two instructions have been added to atomically enable or disable interrupts, and return the previous value of the Status register. These instructions are required in a Release 2 implementation.
- The ability to disable the Count register for highly power-sensitive applications. This enhancement is required in a Release 2 implementation.
- GPR shadow registers: This addition provides the addition of GPR shadow registers and the ability to bind these registers to a vectored interrupt or exception. Shadow registers are an option in Release 2 implementations and the presence of that option is denoted by a non-zero value in SRSCtlHSS. If shadow registers are implemented, either vectored interrupts or support for an external interrupt controller must also be implemented.
- Field, Rotate and Shuffle instructions: These instructions add additional capability in processing bit fields in registers. These instructions are required in a Release 2 implementation.
- Explicit hazard management: This enhancement provides a set of instructions to explicitly manage hazards, in place of the cycle-based SSNOP method of dealing with hazards. These instructions are required in a Release 2 implementation.
- Access to a new class of hardware registers and state from an unprivileged mode. This enhancement is required in a Release 2 implementation.
- Coprocessor 0 Register changes: These changes add or modify CP0 registers to indicate the existence of new and optional state, provide L2 and L3 cache identification, add trigger bits to the Watch registers, and add support for 64-bit performance counter count registers. This enhancement is required in a Release 2 implementation.
- Support for 64-bit coprocessors with 32-bit CPUs: These changes allow a 64-bit coprocessor (including an FPU) to be attached to a 32-bit CPU. This enhancement is optional in a Release 2 implementation.
- New Support for Virtual Memory: These changes provide support for a 1KByte page size. This change is optional in Release 2 implementations, and support is denoted by Config3 (^) SP.
2.2 Compliance and Subsetting .....................................................................................................................................
MIPS32™ Architecture For Programmers Volume I, Revision 2.00 9
2.1.3 Architectural Changes Relative to the MIPS I through MIPS V Architectures
In addition to the MIPS32 Architecture described in this document set, the following changes were made to the architecture relative to the earlier MIPS RISC Architecture Specification, which describes the MIPS I through MIPS V Architectures.
- The MIPS IV ISA added a restriction to the load and store instructions which have natural alignment requirements (all but load and store byte and load and store left and right) in which the base register used by the instruction must also be naturally aligned (the restriction expressed in the MIPS RISC Architecture Specification is that the offset be aligned, but the implication is that the base register is also aligned, and this is more consistent with the indexed load/store instructions which have no offset field). The restriction that the base register be naturally-aligned is eliminated by the MIPS32 Architecture, leaving the restriction that the effective address be naturally-aligned.
- Early MIPS implementations required two instructions separating a mflo or mfhi from the next integer multiply or divide operation. This hazard was eliminated in the MIPS IV ISA, although the MIPS RISC Architecture Specification does not clearly explain this fact. The MIPS32 Architecture explicitly eliminates this hazard and requires that the hi and lo registers be fully interlocked in hardware for all integer multiply and divide instructions (including, but not limited to, the madd, maddu, msub, msubu, and mul instructions introduced in this specification).
- The Implementation and Programming Notes included in the instruction descriptions for the madd, maddu, msub, msubu, and mul instructions should also be applied to all integer multiply and divide instructions in the MIPS RISC Architecture Specification.
2.2 Compliance and Subsetting
To be compliant with the MIPS32 Architecture, designs must implement a set of required features, as described in this document set. To allow flexibility in implementations, the MIPS32 Architecture does provide subsetting rules. An implementation that follows these rules is compliant with the MIPS32 Architecture as long as it adheres strictly to the rules, and fully implements the remaining instructions.Supersetting of the MIPS32 Architecture is only allowed by adding functions to the SPECIAL2 major opcode, by adding control for co-processors via the COP2 , LWC2 , SWC2 , LDC2 , and/or SDC2 , and/or COP3 opcodes, or via the addition of approved Application Specific Extensions. Note, however, that a decision to use the COP3 opcode in an implementation of the MIPS32 Architecture precludes a compatible upgrade to the MIPS64 Architecture because the COP3 opcode is used as part of the floating point ISA in the MIPS64 Architecture.
The instruction set subsetting rules are as follows:
- All CPU instructions must be implemented - no subsetting is allowed.
- The FPU and related support instructions, including the MOVF and MOVT CPU instructions, may be omitted. Software may determine if an FPU is implemented by checking the state of the FP bit in the Config1 CP0 register. If the FPU is implemented, it must include S, D, and W formats, operate instructions, and all supporting instructions. Software may determine which FPU data types are implemented by checking the appropriate bit in the FIR CP register. The following allowable FPU subsets are compliant with the MIPS32 architecture:
- No FPU
- FPU with S, D, and W formats and all supporting instructions
- Coprocessor 2 is optional and may be omitted. Software may determine if Coprocessor 2 is implemented by checking the state of the C2 bit in the Config1 CP0 register. If Coprocessor 2 is implemented, the Coprocessor 2 interface instructions (BC2, CFC2, COP2, CTC2, LDC2, LWC2, MFC2, MTC2, SDC2, and SWC2) may be omitted on an instruction-by-instruction basis.
- Supervisor Mode is optional. If Supervisor Mode is not implemented, bit 3 of the Status register must be ignored on write and read as zero.
- The standard TLB-based memory management unit may be replaced with a simpler MMU (e.g., a Fixed Mapping MMU). If this is done, the rest of the interface to the Privileged Resource Architecture must be preserved. If a
2.4 Architecture Versus Implementation ....................................................................................................................
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2.3.4 MIPS User Defined Instructions (UDIs)
In addition to support for ASEs as described above, the MIPS32 and MIPS64 Architectures define specific instructions for the use of each implementation. The Special2 instruction function fields and Coprocessor 2 are reserved for capability defined by each implementation.
2.4 Architecture Versus Implementation
When describing the characteristics of MIPS processors, architecture must be distinguished from the hardware implementation of that architecture.
- Architecture refers to the instruction set, registers and other state, the exception model, memory management, virtual and physical address layout, and other features that all hardware executes.
- Implementation refers to the way in which specific processors apply the architecture.
Here are two examples:
- A floating point unit (FPU) is an optional part of the MIPS32 Architecture. A compatible implementation of the FPU may have different pipeline lengths, different hardware algorithms for performing multiplication or division, etc.
- Most MIPS processors have caches; however, these caches are not implemented in the same manner in all MIPS processors. Some processors implement physically-indexed, physically tagged caches. Other implement virtually-indexed, physically-tagged caches. Still other processor implement more than one level of cache.
The MIPS32 architecture is decoupled from specific hardware implementations, leaving microprocessor designers free to create their own hardware designs within the framework of the architectural definition.
2.5 Relationship between the MIPS32 and MIPS64 Architectures
The MIPS Architecture evolved as a compromise between software and hardware resources. The architecture guarantees object-code compatibility for User-Mode programs executed on any MIPS processor. In User Mode MIPS processors are backward-compatible with their MIPS32 predecessors. As such, the MIPS32 Architecture is a strict subset of the MIPS64 Architecture. The relationship between the architectures is shown in Figure 2-1.
Figure 2-1 Relationship between the MIPS32 and MIPS64 Architectures
MIPS Architecture
MIPS Architecture
High-performance 32-bit Instruction Set Architecture and Privileged Resource Architecture
High-performance 64-bit Instruction Set Architecture and Privileged Resource Architecture, fully backward compatible with the 32-bit architecture
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Chapter 2 The MIPS Architecture: An Introduction
2.6 Instructions, Sorted by ISA
This section lists the instructions that are a part of the MIPS32 and MIPS64 ISAs.
2.6.1 List of MIPS32 Instructions
Table 2-1 lists of those instructions included in the MIPS32 ISA..
Table 2-1 MIPS32 Instructions
ABS.D ABS.PS^1
- In Release 1 of the Architecture, these instructions are legal only with a MIPS64 processor with 64-bit operations enabled (they are, in effect, actually MIPS64 instructions). In Release 2 of the Architecture, these instructions are legal with either a MIPS32 or MIPS64 processor which includes a 64-bit floating point unit.
ABS.S ADD ADD.D ADD.PS 1 ADD.S ADDI ADDIU ADDU ALNV.PS^1 AND ANDI BC1F BC1FL BC1T BC1TL BC2F BC2FL BC2T BC2TL BEQ BEQL BGEZ BGEZAL BGEZALL BGEZL BGTZ BGTZL BLEZ BLEZL BLTZ BLTZAL BLTZALL BLTZL BNE BNEL BREAK C.cond.D C.cond.PS^1 C.cond.S CACHE CEIL.L.D 1 CEIL.L.S^1 CEIL.W.D CEIL.W.S CFC1 CFC CLO CLZ COP2 CTC1 CTC2 CVT.D.L^1 CVT.D.S CVT.D.W CVT.L.D 1 CVT.L.S^1 CVT.PS.S^1 CVT.S.D CVT.S.L^1 CVT.S.PL^1 CVT.S.PU^1 CVT.S.W CVT.W.D CVT.W.S DERET DI^2
- These instructions are legal only in an implementation of Release 2 of the Architecture
DIV DIV.D DIV.S DIVU EHB^2 EI 2 ERET EXT 2 FLOOR.L.D 1 FLOOR.L.S^1 FLOOR.W.D FLOOR.W.S INS 2 J JAL JALR JALR.HB^2 JR JR.HB 2 LB LBU LDC1 LDC2 LDXC1^1 LH LHU LL LUI LUXC1 1 LW LWC1 LWC2 LWL LWR LWXC1^1 MADD MADD.D^1 MADD.PS 1 MADD.S 1 MADDU MFC0 MFC1 MFC2 MFHC1^2 MFHC2^2 MFHI MFLO MOV.D MOV.PS 1 MOV.S MOVF MOVF.D MOVF.PS^1 MOVF.S MOVN MOVN.D MOVN.PS^1 MOVN.S MOVT MOVT.D MOVT.PS 1 MOVT.S MOVZ MOVZ.D MOVZ.PS^1 MOVZ.S MSUB MSUB.D 1 MSUB.PS^1 MSUB.S 1 MSUBU MTC0 MTC1 MTC2 MTHC1^2 MTHC2^2 MTHI MTLO MUL MUL.D MUL.PS^1 MUL.S MULT MULTU NEG.D NEG.PS 1 NEG.S NMADD.D^1 NMADD.PS^1 NMADD.S^1 NMSUB.D 1 NMSUB.PS^1 NMSUB.S 1 NOR OR ORI PLL.PS 1 PLU.PS 1 PREF PREFX^1 PUL.PS 1 PUU.PS 1 RDHWR 2 RDPGPR^2 RECIP.D 1 RECIP.S^1 ROTR^2 ROTRV^2 ROUND.L.D^1 ROUND.L.S 1 ROUND.W.D ROUND.W.S RSQRT.D^1 RSQRT.S 1 SB SC SDBBP SDC1 SDC2 SDXC1^1 SEB^2 SEH^2 SH SLL SLLV SLT SLTI SLTIU SLTU SQRT.D SQRT.S SRA SRAV SRL SRLV SSNOP SUB SUB.D SUB.PS^1 SUB.S SUBU SUXC1^1 SW SWC1 SWC2 SWL SWR SWXC1^1 SYNC SYNCI 2 SYSCALL TEQ TEQI TGE TGEI TGEIU TGEU TLBP TLBR TLBWI TLBWR TLT TLTI TLTIU TLTU TNE TNEI TRUNC.L.D 1 TRUNC.L.S^1 TRUNC.W.D TRUNC.W.S WAIT WRPGPR^2 WSBH^2 XOR XORI
