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UNIT 3 FIELD EFFECT TRANSISTOR
JFET
JFET is a unipolar-transistor, which acts as a voltage controlled current device and is a device in which current at two electrodes is controlled by the action of an electric field at a p-n junction. A JFET, or junction field-effect transistor, or JUGFET, is a FET in which the gate is created by reverse-biased junction (as opposed to the MOSFET which creates a junction via a field generated by conductive gate, separated from the gate region by a thin insulator).
Construction n-channel JFET The figure shows construction and symbol of n-channel JFET. A small bar of extrinsic semiconductor material, n type is taken and its two ends, two ohmic contacts are made which is the drain and source terminals of FET. Heavily doped electrodes of p type material form p-n junctions on each side of the bar. The thin region between the two p gates is called the channel. Since this channel is in the n type bar, the FET is known as n-channel JFET.
The electrons enter the channel through the terminal called source and leave through the terminal called drain. The terminals taken out from heavily doped electronics of p type material are called gates. These electrodes are connected together and only one terminal is taken out, which is called gate, as shown in the figure. p-channel JFET The device could be made of p type bar with two n type gates as shown in the figure. This will be p-channel JFET. The principle of working of n-channel JFET and p- channel JFET are similar. The only difference being that in n-channel JFET the current is carried by electrons while in p-channel JFET, it is carried by holes.
Operation In JFET, the p-n junction between gate and source is always kept in reverse biased conditions. Since the current in a reverse biased p-n junction is extremely small, practically zero. The gate current in JFET is often neglected and assumed to be zero.
the fig it can be observed that depletion region width is more at the drain side as compared to source side because near the junction, voltage at drain side is more than the voltage at the source side. This shows that reverse bias is not uniform near the junction as it gradually increases from source side to drain side. The depletion region does not contain charge carriers. The space between two depletion regions is available for conducting portion of the channel. When reverse bias voltage is applied externally to the gate, the reverse bias will increase and hence increase the penetration of the depletion region which reduces the width of the conducting portion of the channel. When the width of the conducting portion of the channel reduces, the no. of electrons flowing from source to drain reduces and hence the current flowing from drain to source reduces. When the external reverse bias voltage at the gate is increased as shown in fig (b) & (c) the depletion regions will increase more and at a particular stage the width of the depletion region will be equal to the original width of the depletion regions will increase more and more, and stage will come when the width of the depletion regions will be equal to the original width of the channel, leaving zero width for conducting portion of the channel, as shown in the fig (c). This will prevent any current flow from drain to source and this will cut off the drain current. The gate to source voltage that produces cutoff is known as cutoff voltage (VGS (OFF)). When the gate is shorted to source, there is minimum reverse bias between gate and source p-n junction, making depletion region width minimum and conducting channel width maximum. In this case maximum drain current flows which is designated by IDSS and this is the possible drain current in JFET. It is clear that the gate to source voltage controls the current flowing through the channel and hence FET is also called voltage controlled current source. Characteristics Drain (or) current voltage characteristics of JFET The current voltage characteristics of an n-channel JFET is shown in the figure. The drain current (ID) is plotted with VDS for different values of VGS. This characteristic is also known as drain characteristics of JFET. From the fig, we see that as the voltage increased from 0 to a few volts, the current increases as determined by ohm’s law. The
straight nature of the curve at low values for VDS reveals that for this region the resistance is essentially constant for a fixed valued of VGS. But the slope of the ID - VDS curve near the origin is a function of the gate voltage. This region of operation is known as the linear region or ohmic region. As VDS increases and approaches a value VP (referred to as pinch – off voltage), slope of the curve changes and the channel resistance increases. If VDS increases beyond pinch-off value, characteristics curve becomes more horizontal and ID maintains a saturation level. For VGS = 0v , the saturated value of ID is designated as IDSS , which is the drain – to – source current with source – gate short circuit. Thus, IDSS is the maximum drain current for a JFET, obtained under the conditions VGS = 0V and VDS > |VP|. As the VDS increases beyond VP, the level of ID remains essentially the same and this region of the characteristics is known as saturation region. It may also be noted that once VDS > Vp, the JFET has the characteristics of a current source. Thus the current – voltage characteristics displayed in fig can be divided into ohmic (linear) and saturation regions with the pinch-off condition as the boundary.
As the negative bias of VGS increases, depletion region forms similar to those to those with VGS = 0 V but at a lower level of VDS. Thus, the result of applying a negative bias to the gate is to reach the saturation level at a lower level of VDS, as shown in the
Expression for pinch off voltage and Drain Current For the transfer characteristics,VDS is maintained constant at a suitable value greater than the pinch off voltage VP.The gate voltage VGS is decreased from zero till ID is reduced to zero. The transfer characteristics ID versus VGS are shown in figure.
Where IDS is the saturation drain current, IDSS is the value of IDS when VGS=0 and VP is the pinch off voltage Differentiating eqn (1) with respect to VGS we obtain the expression of gm
gm= -2 IDSS/VP(1- VGS/VP) (2) From eqn (1) (1-VGS/VP)= (IDS/IDSS)1/2^ (3) Suppose gm=gm0 when vGS= gmo=-2IDSS/VP (4) Therefore from eqn (2) and (4) gm=gm0(1-VGS/VP)
MOSFET MOSFET stands for metal oxide semiconductor field effect transistor. It is capable of voltage gain and signal power gain. The MOSFET is the core of integrated circuit designed as thousands of these can be fabricated in a single chip because of its very small size. Every modern electronic system consists of VLST technology and without MOSFET, large scale integration is impossible. It is a four terminals device. The drain and source terminals are connected to the heavily doped regions. The gate terminal is connected top on the oxide layer and the substrate or body terminal is connected to the intrinsic semiconductor. MOSFET has four terminals which is already stated above, they are gate, source drain and substrate or body. MOS capacity present in the device is the main part. The conduction and valance bands are position relative to the Fermi level at the surface is a function of MOS capacitor voltage. The metal of the gate terminal and the sc acts the parallel and the oxide layer acts as insulator of the state MOS capacitor. Between the drain and source terminal inversion layer is formed and due to the flow of carriers in it, the current flows in MOSFET the inversion layer is properties are controlled by gate voltage. Thus it is a voltage controlled device. Two basic types of MOSFET are n channel and p channel MOSFETs. In n channel MOSFET is current is due to the flow of electrons in inversion layer and in p channel current is due to the flow of holes. Another type of characteristics of clarification can be made of those are enhancement type and depletion type MOSFETs. In enhancement mode, these are normally off and turned on by applying gate voltage. The opposite phenomenon happens in depletion type MOSFETs.
also attracts holes from p+ source and drain region in to the channel region. Thus hole which channel is formed now if a voltage between the source and the drain is applied current flows. The gate voltage controls the hole concentration of the channel. The diagram of p- channel enhancement and depletion MOSFET are given below.
N-Channel MOSFET MOSFET having n-channel region between source and drain is known as n-channel MOSFET. It is a four terminal device, the terminals are gate, drain and source and substrate or body. The drain and source are heavily doped n+ region and the substrate is p-type. The current flows due to flow of the negatively charged electrons, that’s why it is known as n- channel MOSFET. When we apply the positive gate voltage the holes present beneath the oxide layer experiences repulsive force and the holes are pushed downwards in to the bound negative charges which are associated with the acceptor atoms. The positive gate voltage also attracts electrons from n+ source and drain region in to the channel thus an electron reach channel is formed, now if a voltage is applied between the source and drain. The gate voltage controls the electron concentration in the channel n-channel MOSFET is preferred over p-channel MOSFET as the mobility of electrons are higher than holes. The diagrams of enhancements mode and depletion mode are given below.
Enhancement and Depletion Mode MOSFET EMOSFET Symbol
to the source terminal, there is zero voltage across the source substrate junction, and the–drain-substrate junction remains reverse biased. When the gate is made positive with respect to the source and the substrate, negative (i.e. minority) charge carriers within the substrate are attracted to the positive gate and accumulate close to the-surface of the substrate. As the gate voltage is increased, more and more electrons accumulate under the gate. Since these electrons cannot flow across the insulated layer of silicon dioxide to the gate, so they accumulate at the surface of the substrate just below the gate. These accumulated minority charge carriers N - type channel stretching from drain to source. When this occurs, a channel is induced by forming what is termed an inversion layer (N-type). Now a drain current starts flowing. The strength of the drain current depends upon the channel resistance which, in turn, depends upon the number of charge carriers attracted to the positive gate. Thus drain current is controlled by the gate potential. Since the conductivity of the channel is enhanced by the positive bias on the gate so this device is also called the enhancement MOSFET or E- MOSFET. The minimum value of gate-to-source voltage VGS that is required to form the inversion layer (N-type) is termed the gate-to-source threshold voltage VGST. For VGS below VGST, the drain current ID = 0. But for VGS exceeding VGST an N-type inversion layer connects the source to drain and the drain current ID is large. Depending upon the device being used, VGST may vary from less than 1 V to more than 5 V. JFETs and DE-MOSFETs are classified as the depletion-mode devices because their conductivity depends on the action of depletion layers. E-MOSFET is classified as an enhancement-mode device because its conductivity depends on the action of the inversion layer. Depletion-mode devices are normally ON when the gate-source voltage VGS = 0, whereas the enhancement-mode devices are normally OFF when VGS = 0. Characteristics Drain Characteristics Drain characteristics of an N-channel E-MOSFET are shown in figure. The lowest curve is the VGST curve. When VGS is lesser than VGST, ID is approximately zero. When VGS is greater than VGST, the device turns- on and the drain current ID is controlled by
the gate voltage. The characteristic curves have almost vertical and almost horizontal parts.
The almost vertical components of the curves correspond to the ohmic region, and the horizontal components correspond to the constant current region. Thus E-MOSFET can be operated in either of these regions i.e. it can be used as a variable-voltage resistor (WR) or as a constant current source. Transfer Characteristics Figure shows a typical transconductance curve. The current IDSS at VGS <=0 is very small, being of the order of a few nano-amperes. When the VGS is made positive, the drain current ID increases slowly at first, and then much more rapidly with an increase in VGS. The manufacturer sometimes indicates the gate-source threshold voltage VGST at which the drain current ID attains some defined small value, say 10 u A. A current ID (0N, corresponding approximately to the maximum value given on the drain characteristics and the values of VGS required to give this current VGs QN are also usually given on the manufacturers data sheet.
Construction
Fig 5.1 Depletion Mode N Channel MOSFET The depletion mode MOSFET shown as a N channel device (P channel is also available) in Fig 5.1 is more usually made as a discrete component, i.e. a single transistor rather than IC form. In this device a thin layer of N type silicon is deposited just below the gate−insulating layer, and forms a conducting channel between source and drain. Therefore when the gate source voltage VGS is zero, current (in the form of free electrons) can flow between source and drain. Note that the gate is totally insulated from the channel by the layer of silicon dioxide. Now that a conducting channel is present the gate does not need to cover the full width between source and drain. Because the gate is totally insulated from the rest of the transistor this device, like other IGFETs, has a very high input resistance. Operation In the N channel device, shown in Fig. 5.2 the gate is made negative with respect to the source, which has the effect of creating a depletion area, free from charge carriers, beneath the gate. This restricts the depth of the conducting channel, so increasing channel resistance and reducing current flow through the device. Depletion mode MOSFETS are also available in which the gate extends the full width of the channel
(from source to drain). In this case it is also possible to operate the transistor in enhancement mode. This is done by making the gate positive instead of negative.
Fig. 5.2 Operation of a Depletion Mode MOSFET The positive voltage on the gate attracts more free electrons into the conducing channel, while at the same time repelling holes down into the P type substrate. The more positive the gate potential, the deeper, and lower resistance is the channel. Increasing positive bias therefore increases current flow. This useful depletion/enhancement version has the disadvantage that, as the gate area is increased, the gate capacitance is also larger than true depletion types. This can present difficulties at higher frequencies. Handling Precautions for MOSFET The MOSFET has the drawback of being very susceptible to overload voltage and may require special handling during installation. The MOSFET gets damaged easily if it is not properly handled. A very thin layer of SiO 2 , between the gate and channel is damaged due to high voltage and even by static electricity. The static electricity may result from the sliding of a device in a plastic bag. If a person picks up the transistor by its case and brushes the gate against some grounded objects, a large electrostatic discharge may result.In a relatively dry atmosphere, a static potential of 300V is not uncommon on a person who has high resistance soles on his footwear.
each and the sorce is placed a back-to-back (or front-to-front)pair of diodes, which are built right into P type substrate. FET as Voltage-Variable Resistor FET is operated in the constant-current portion of its output characteristics for the linear applications. In the region before pinch-off , where VDS is small , the drain to source resistance rd can be controlled by the bias voltage VGS. The FET is useful as a voltage variable resistor (VVR) or voltage dependent resistor (VDR). In JFET , the drain to source conductance gd =ID/VDS for small values of VDS , which may also be expressed as gd=g (^) do [1-(VGS/VP)1/2] where gdo is the value of drain conductance when the bias voltage VGS is zero. The variation of the rd with VGS can be closely approximated by the empirical expression , rd =ro/(1-KVGS) Where ro=drain resistance at zero gate bias, and K=a constant , dependent upon FET type. Comparison of MOSFET and JFET
- In enhancement and depletion types of MOSFET, the transverse electric field induced across an insulating layer deposited on the semiconductor material controls the conductivity of the channel. In the JFET the transverse electric field across the reverse biased PN junction controls the conductivity of the channel.
- The gate leakage current in a MOSFET is of the order of 10-12A.Hence the input resistance of a MOSFET is very high in the order of 10^10 to 10^15 ohm. The gate leakage current of a JFET is of the order of 10-9A and its input resistance is of the order of 10^8 ohm.
- The output characteristics of the JFET are flatter than those of the MOSFET and hence, the drain resistance of a JFET(0.1 to 1Mohm) is much higher than that of a MOSFET(1 to 50 K ohm)
- JFETs are operated only in the depletion mode. The depletion type MOSFET may be operated in both depletion and enhancement mode.
- Comparing to JFET, MOSFETs are easier to fabricate.
- MOSFET is very susceptible to overload voltage and needs special handling during installation. It gets damaged easily if it is not properly handled.
- MOSFET has zero offset voltage. As it is a symmetrical device, the source and drain can be interchanged. These two properties are very useful in analog signal switching.
- Special digital CMOS circuits are available which involves near – zero power dissipation and very low voltage and current requirements. This makes them most suitable for portable systems. Comparison of JFET And BJT
- FET operations depend only on the flow of majority carrier-holes for P-channel FETs and electrons for N-channel FETs. Therefore, they are called Unipolar devices. Bipolar transistor (BJT) operation depends on both minority and majority current carrier.
- As FET has no junctions and the conduction is through an N-type or P-type semiconductor material, FET is less noisy than BJT.
- As the input circuit of FET is reverse biased, FET exhibits as much higher input impedance (in the order of 100MOHM) and lower output impedance and there will be a high degree of isolation between input and output. So, FET can act as excellent buffer amplifier but the BJT has low input impedance because its input circuit is forward biased.
- FET is a voltage control device, i.e. voltage at the input terminal controls the output current, whereas BJT is a current control device, i.e. the input current controls the output current.
- FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less space than BJTs.
- The performance of BJT is degraded by neutron radiations because of reduction in minority carrier life time, whereas FET can tolerate a much higher level of radiation since they do not rely on minority carrier for their operation.
- The performance of FET is relatively unaffected by ambient temperature changes. As it has a negative temperature coefficient at high current levels, it
