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Lab Assignment 1 - PS 2, PC Keyboard Interface - Spring 2005 | EE 422, Assignments of Electrical and Electronics Engineering

Material Type: Assignment; Class: ADVANCED LOGIC DESIGN; Subject: Electrical Engineering; University: University of Alabama - Huntsville; Term: Unknown 1989;

Typology: Assignments

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CPE/EE 422/522, Laboratory Assignment 1
PS 2, PC Keyboard Interface
(CPE/EE 422 Students 5% of Final Grade -- CPE/EE 522 Students 2.5% of Final Grade)
The purpose of this laboratory project is to give each student the opportunity to develop a practi-
cal logic design that interfaces a 104 key PS-2 style keyboard to the Altera UP 2 Educational
Trainer. The design should be created in a manner that will allow it to display in hexadecimal for-
mat on two seven-segment LEDs, the ANSII encoding that correspond to each key that is pressed.
Background
PS-2 type keyboards contain the embedded logic necessary to scan all 104 keys, produce a unique
keyboard scan code for each key that is pressed, and to send this scan code value to another device
in a serial manner. (A hardware realization of this embedded logic will be the focus of the scan-
ning keypad design that is to be developed in Laboratory Assignment 3. The focus of this labora-
tory, though, is not to implement this low-level logic but rather be able to decode the scan code
after it is sent out in serial form and then convert this code to an ANSII representation and display
it on the seven segment LEDs.) The PS-2 type interface includes four main signals that include
VCC, Ground, a keyboard clock, and a keyboard data line. The VCC and ground line are used to
power the keyboard and data is transferred in and out of the keyboard using the bidirectional key-
board clock (KEY_CLK) and data (DATA) lines. In this lab, we will use the keyboard as an out-
put only device meaning the from our digital design’s point of view the keyboard clock and
keyboard data lines are always inputs to the design. (It is possible, and common, for an external
design to drive these lines in the other direction to perform such functions as resetting the key-
board, switching keyboards scan code character sets, etc. The keyboard is very flexible. We will
only be using its basic default features in this laboratory assignment.)
In its default mode, every time a key is pressed a sequence of bytes is sent serially across the data
line from the keyboard to the external device. There is a separate sequence of bytes that is sent
when each key is pressed and another sequence that is sent when each key is released. The
sequence that is sent when the key is pressed is often called the Make Code and the sequence that
is sent when the key is released is called the Break Code. Except for a few special keys, the last
byte that is sent in the make code and break code sequence for a given key are identical to one
another with its value uniquely represents the key that was pressed. Table 1 lists the final byte of
the make/break sequences for each of the keys on the PS/2 keyboards that will be used in the lab-
oratory assignment. This table assumes the key labeling that is shown in Figure 1.
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CPE/EE 422/522, Laboratory Assignment 1

PS 2, PC Keyboard Interface

(CPE/EE 422 Students 5% of Final Grade -- CPE/EE 522 Students 2.5% of Final Grade)

The purpose of this laboratory project is to give each student the opportunity to develop a practi- cal logic design that interfaces a 104 key PS-2 style keyboard to the Altera UP 2 Educational Trainer. The design should be created in a manner that will allow it to display in hexadecimal for- mat on two seven-segment LEDs, the ANSII encoding that correspond to each key that is pressed.

Background

PS-2 type keyboards contain the embedded logic necessary to scan all 104 keys, produce a unique keyboard scan code for each key that is pressed, and to send this scan code value to another device in a serial manner. (A hardware realization of this embedded logic will be the focus of the scan- ning keypad design that is to be developed in Laboratory Assignment 3. The focus of this labora- tory, though, is not to implement this low-level logic but rather be able to decode the scan code after it is sent out in serial form and then convert this code to an ANSII representation and display it on the seven segment LEDs.) The PS-2 type interface includes four main signals that include VCC, Ground, a keyboard clock, and a keyboard data line. The VCC and ground line are used to power the keyboard and data is transferred in and out of the keyboard using the bidirectional key- board clock (KEY_CLK) and data (DATA) lines. In this lab, we will use the keyboard as an out- put only device meaning the from our digital design’s point of view the keyboard clock and keyboard data lines are always inputs to the design. (It is possible, and common, for an external design to drive these lines in the other direction to perform such functions as resetting the key- board, switching keyboards scan code character sets, etc. The keyboard is very flexible. We will only be using its basic default features in this laboratory assignment.)

In its default mode, every time a key is pressed a sequence of bytes is sent serially across the data line from the keyboard to the external device. There is a separate sequence of bytes that is sent when each key is pressed and another sequence that is sent when each key is released. The sequence that is sent when the key is pressed is often called the Make Code and the sequence that is sent when the key is released is called the Break Code. Except for a few special keys, the last byte that is sent in the make code and break code sequence for a given key are identical to one another with its value uniquely represents the key that was pressed. Table 1 lists the final byte of the make/break sequences for each of the keys on the PS/2 keyboards that will be used in the lab- oratory assignment. This table assumes the key labeling that is shown in Figure 1.

Table 1: Make/Break Keyboard Scan Codes for the PS/2 Keyboard

Key # Final Byte of Make/ Break Sequence

Key # Final Byte of Make/ Break Sequence

Key # Final Byte of Make/ Break Sequence

1 76 36 4A 71 6B 2 05 37 7C 72 73 3 06 38 7B 73 74 4 04 39 0D 74 79 5 0C 40 15 75 12 6 03 41 1D 76 1A 7 0B 42 24 77 22 8 83 43 2D 78 21 9 0A 44 2C 79 2A 10 01 45 35 80 32 11 09 46 3C 81 31 12 78 47 43 82 3A 13 07 48 44 83 41 14 7C 49 4D 84 49 15 7E 50 54 85 4A 16 77 51 5B 86 59 17 0E 52 5A 87 75 18 16 53 71 88 69 19 1E 54 69 89 72 20 26 55 7A 90 7A 21 25 56 6C 91 5A 22 2E 57 75 92 14 23 36 58 7D 93 1F 24 3D 59 58 94 11 25 3E 60 1C 95 29 26 46 61 1B 96 11 27 45 62 23 97 27 28 4E 63 2B 98 2F 29 55 64 34 99 14 30 5D 65 33 100 6B 31 66 66 3B 101 72 32 70 67 42 102 74 33 6C 68 4B 103 70 34 7D 69 4C 104 71 35 77 70 52

In this assignment students are to develop a design that will display in hexadecimal the ASCII encoding that represents the key that has been pressed. The ASCII value that is displayed will be derived from the last byte of each make/break code value that is sent from the keyboard each time a key is pressed or released. The ASCII values for the upper-case letters A through Z, the numbers 0 through 9, and all punctuation marks should be displayed whenever a key is pressed or released. The function keys and other keys (such as the shift, ctrl, and Scroll Lock should simply display the ASCII null value of 00 on the two seven segment display that are driven by the FLEX EPF10K20 device.

The pins for the segments of the two seven segment displays are shown in the Table 3 below:

Assignment

There are to be two separate designs that are to be developed and demonstrated. The first is to be schematic capture-based with only the keyboard scan code to ASCII conversion and binary to seven segment hexadecimal conversion sections of the design being implemented in VHDL. The second design should be entered entirely in VHDL. Both designs must be downloaded to the UP-2 educational board, demonstrated to the lab instructor and be fully documented in the manner outlined in the Laboratory Report Handout. Your laboratory instructor will demonstrate to you how to download the design through the JTAG port to the UP-2 board.

Due Week of 2/06/07 -- 2/12/

Table 2: Altera Pin Numbers for the PS/2 Keyboard and Clock Lines

Line Pin Numbers

KEY_CLK 30

DATA 31

Table 3: Altera Pin Numbers for the FLEX DIGIT Segment I/O Connections Display Segment Pin Numbers Left Display

Pin Numbers Right Display a 6 17 b 7 18 c 8 19 d 9 20 e 11 21 f 12 23 g 13 24 Decimal Point 14 25