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Electronic devices and circuits experimental lab
Typology: Summaries
Uploaded on 11/16/2019
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Faculty Member: ______Saqib Nazir____ Dated: 20-10-19
Semester:___3rd__________ Section: _____B________
Name Reg. No Viva / Quiz / Lab Performan ce
Analysis of data in Lab Report
Modern Tool Usage
Ethics and Safety
Individual and Team Work
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks Maryam Mahmood 257913
Iram Fatima Aulakh 249796
Sahar Zahid 257831
The following components, test equipment and software would be required.
The experiment is broken down in two exercises; one of the experiment is divided into two parts namely:simulation and implementation. You are required to observe and record the simulation/ implementation results and answer the given questions. Include your answers in your lab reports.
In this part of the experiment you will be given a sample transistor and using the procedure below you are required to determine whether the transistor is an NPN or PNP transistor. You are also required to identify the terminals of the transistor.
Procedure
The emitter-base PN junction has a slightly greater forward voltage drop than the collector- base PN junction, because of heavier doping of the emitter semiconductor layer
As 2-3 and 2-1 are both positive voltages (from table), so we can say that 2 is base and it’s a p- type region. Hence our transistor is an NPN type transistor.
In this part the students will study the common emitter I-V characteristics of a BJT. In particular relationship between the collector current and the voltage that appears across the collector- emitter junction of the transistor will be observed. Further, the effect of various parameters like, saturation current, early voltage etc. on the transistor I-V characteristics will be studied.
Procedure:
Saturated region
Active regionCut-off region
Because of Early Effect, as VCE increases, i (^) c also increases. This is known as early effect which is responsible for the slope in the graph.
x 1 = 9.507 V x 2 = 14.335 V y 1 = 2.6004 mA y 2 = 2.7500 mA
m = =^ 0.
So; y = mx +c y = 0.031x + c c = 2.*
Figure 2B – Circuit Diagram for Implementation-II
V (^) BB (V) VCC (V ) I (^) B (uA) I (^) C (uA) VCE (V) Beta 0.4 4 0.62 2.11 4.0190 3. 5 0.63 1.69 5.0655 2. 6 0.18 1.66 6.063 9. 7 0.12 1.15 7.020 9. 8 0.10 0.20 8.072 2 9 0.07 0.18 9.051 2. 0.5 4 0.01 0.16 3.969 16 5 0.03 0.17 4.905 5. 6 0.01 0.17 5.908 17 7 0.02 0.19 6.785 9. 8 0.07 0.15 7.990 2. 9 0.05 0.20 8.972 4 0.6 4 0.37 1.54 3.945 4. 5 0.38 1.51 4.988 3. 6 0.38 1.48 5.936 3. 7 0.37 1.45 6.963 3. 8 0.356 1.41 8.076 4. 9 0.372 1.43 8.945 3. 0.7 4 3.912 506 3.69 129. 5 3.962 542 4.86 136. 6 3.978 559 5.89 140. 7 3.995 565 6.933 141. 8 4.068 587 7.89 144. 9 4.099 609 8.86 148.
Answer the following questions:
The graphs are not entirely similar as in implementation, we have only graphed the transistor in active mode while in simulation, we’ve graphed it in saturation mode too.
x 1 = 4.860 V x 2 = 7.89 V y 1 = 565 uA y 2 = 587 uA
m = =^ 7.
So; y = mx +c y = 7.26x + c c = 529*
For VA , putting y = 0;
0 = 7.26 VA + 529 VA =* = - 72.8 V
The values are approximately same.