Understanding Latches, Flip-Flops, and Bit Storage in Digital Logic, Slides of Computer Aided Design (CAD)

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Latches & Flip-Flops

Combinational Logic (Review)

• Changes in input values are reflected immediately (subject to the speed of light and electrical delays) on the outputs
• Each gate has an associated “electrical delay”
• Delays are often ignored for the purpose of the logic design (but not for the real implementation!)
• As soon as inputs change, the outputs change – no memory of what happened before - (at least conceptually)

Simple Memory Element

• Must provide a feedback loop to allow memory of current state
• How do you control the memory – load it, change it, clear it?? - Take CS 278 (or check out the Appendix)

A B

Master-Slave D Flip-Flop

• A state element that is edge-sensitive
  • Want changes in output ONLY on the transition of the Clk signal from 0  1 (or from 1  0)

D Q Q

positive edge-triggered flip-flop

Registers

• A flip-flop stores one bit of information
• When you want to store n bits  register
  • n flip-flops used
  • Clock is shared by all so action is synchronous with clock edge
• Some common register types
  • Simple register
  • Shift register
  • Parallel access shift register
  • Lots of counters: up counter, down counter, BCD counter, ring counter, Johnson counter

Simple 4 Bit Register

• A standard 4 bit register using D flip flops

Q 3 Q 2 Q 1 Q (^0)

Clock

Parallel input

Parallel output

D Q

Q

D Q

Q

D Q

Q

D Q

Q