Binary Arithmetic: 2's Complement, Multiplication, Division and Representations, Slides of Number Theory

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2’s Complement – Signed Numbers^ 0000 0000 0000 0000 0000 0000 0000 0000

= 0two ten 0000 0000 0000 0000 0000 0000 0000 0001

= 1two ten …0111 1111 1111 1111 1111 1111 1111 1111

(^31) = 2-1two 1000 0000 0000 0000 0000 0000 0000 0000

(^31) = -2two 1000 0000 0000 0000 0000 0000 0000 0001

(^31) = -(2– 1)two 1000 0000 0000 0000 0000 0000 0000 0010

(^31) = -(2– 2)two …1111 1111 1111 1111 1111 1111 1111 1110

= -2two 1111 1111 1111 1111 1111 1111 1111 1111

= -1two Why is this representation favorable?Consider the sum of 1 and -2 …. we get -1Consider the sum of 2 and -1 …. we get +1This format can directly undergo addition without any conversions!Each number represents the quantity^31 x-2^ + x^231

30 29 + x^2 + … + x^29

1 02 + x^2 1

Addition and Subtraction^ • Addition is similar to decimal arithmetic• For subtraction, simply add the negative number – hence,subtract A-B involves negating B’s bits, adding 1 and A

Overflows^ • For an unsigned number, overflow happens when the last carry (1)cannot be accommodated• For a signed number, overflow happens when the most significant bitis not the same as every bit to its left^ ^ when the sum of two positive numbers is a negative result^ ^ when the sum of two negative numbers is a positive result^ ^ The sum of a positive and negative number will never overflow• MIPS allows addu and subu instructions that work with unsignedintegers and never flag an overflow – to detect the overflow, otherinstructions will have to be executed

HW Algorithm 1^ In every step• multiplicand is shifted• next bit of multiplier is examined (also a shifting step)• if this bit is 1, shifted multiplicand is added to the product

HW Algorithm 2^ • 32-bit ALU and multiplicand is untouched• the sum keeps shifting right• at every step, number of bits in product + multiplier = 64,hence, they share a single 64-bit register

MIPS Instructions^ mult^ $s2, $s

computes the product and storesit in two “internal” registers thatcan be referred to as hi and lo

mfhi^ $s^

moves the value in hi into $s

mflo^ $s^

moves the value in lo into $s

Similarly for multu

Fast Algorithm

• The previous algorithmrequires a clock to ensure thatthe earlier addition hascompleted before shifting• This algorithm can quickly setup most inputs – it then has towait for the result of each addto propagate down – fasterbecause no clock is involved-- Note: high transistor cost

Division

1001 Quotientten^

Divisor^1000

|^1001010 ten^

Dividendten^

^0001000000

^0000100000

^0000001000

Quo:^0

At every step,• shift divisor right and compare it with current dividend• if divisor is larger, shift 0 as the next bit of the quotient• if divisor is smaller, subtract to get new dividend and shift 1as the next bit of the quotient

Divide Example^ • Divide 7^ (0000 0111ten^

) by 2(0010twoten^

)two Initial values 0 1 2 3 4 5

RemainderDivisor Quot Step Iter

Hardware for Division^ A comparison requires a subtract; the sign of the result isexamined; if the result is negative, the divisor must be added back

Efficient Division

Convention: Dividend and remainder have the same signQuotient is negative if signs disagreeThese rules fulfil the equation above

• Lecture 8: Binary Multiplication & Division • Today’s topics:
  Addition/Subtraction
  Multiplication
  Division• Reminder: get started early on assignment
• Divisions involving Negatives • Simplest solution: convert to positive and adjust sign later• Note that multiple solutions exist for the equation:Dividend = Quotient x Divisor + Remainder+7 div +
• Quo = +
• Rem = +
• -7 div +
• Quo = -
• Rem = -
• +7 div -
• Quo = -
• Rem = +
• -7 div -
• Quo = +
• Rem = -

Title^ • Bullet