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MICROPROCESSOR AND INTERFACING
UNIT I
HISTORY OF MICROPROCESSORS
Introduction 4-Bit Microprocessors 8-Bit Microprocessors 16-Bit Microprocessors 32-Bit Microprocessors 64-Bit Microprocessors
INTRODUCTION Fairchild Semiconductors (founded in 1957) invented the first IC in 1959. In 1968, Robert Noyce, Gordan Moore, AndrewGrove resigned from Fairchild Semiconductors. They founded their own company Intel (Integrated Electronics). Intel grown from 3 man start-up in 1968 to industrial giant by 1981. It had 20,000 employees and $188 million revenue.
4-BIT MICROPROCESSORS Introduced in 1971. It was the first. microprocessor by Intel. It was a 4-bit μP. Its clock speed was 740KHz. It had 2, transistors. It could execute around 60,000 instructions per second. INTEL 4040 Introduced in 1974. It was also 4-bit μP.
8-BIT MICROPROCESSORS
Introduced in 1972. It was first 8-bit μP Its clock speed was 500 KHz. Could execute 50,000 instructions per second. INTEL 8080 Introduced in 1974. It was also 8-bit μP. Its clock speed was 2 MHz. It had 6,000 transistors. Was 10 times faster than 8008. Could execute 5,00, instructions per second. INTEL 8085 Introduced in 1976. It was also 8-bit μP. Its clock speed was 3 MHz. Its data bus is 8-bit and address bus is 16-bit. It had 6,500 transistors. Could execute 7,69,230 instructions per second. It could access 64 KB of memory. It had 246 instructions.
16-BIT MICROPROCESSORS
INTEL 8086 Introduced in 1978. It was first 16- bit μP. Its clock speed is 4.77 MHz, 8 MHz and 10 MHz, depending on the version. Its data bus is 16-bit and address bus is 20-bit. It had 29,000 transistors. Could execute 2.5 million instructions per second. It could access 1 MB of memory. It had 22,000 instructions. It had Multiply and Divide instructions. INTEL 8088 Introduced in 1979. It was also 16-bit μP. It was created as a cheaper version of Intel’s 8086. It was a 16-bit processor with an 8-bit external bus. Could execute 2.5 million instructions per second. This chip became the most popular in the computer industry when IBM used it for its first PC. INTEL 80186 & 80188 Introduced in 1982. They were 16-bit μPs. Clock speed was 6 MHz. 80188 was a cheaper version of 80186 with an 8- bit external data bus. They had additional components like: Interrupt Controller Clock Generator Local Bus Controller Counters. INTEL 80286 Introduced in 1982. It was 16-bit μP. Its clock speed was 8 MHz. Its data bus is 16-bit and address bus is 24-bit. It could address 16 MB of memory. It had 1,34,000 transistors. It could execute 4 million instructions per second.
32-BIT MICROPROCESSORS
INTEL 80386 Introduced in 1986. It was first 32-bit μP. Its data bus is 32-bit and address bus is 32-bit. It could address 4 GB of memory. It had 2,75,000 transistors. Its clock speed varied from 16 MHz to 33 MHz depending upon the various versions. Different versions: 80386 DX 80386 SX 80386 SL Intel 80386 became the best selling microprocessor in history. INTEL 80486 Introduced in 1989. It was also 32-bit μP. It had 1. million transistors. Its clock speed varied from 16 MHz to 100 MHz depending upon the various versions. It had five different versions: 80486 DX, 80486 SX, 80486 DX2, 80486 SL, 80486 DX4, 8 KB of cache memory was introduced. INTEL PENTIUM Introduced in 1993. It was also 32-bit μP. It was originally named 80586. Its clock speed was 66 MHz. Its data bus is 32-bit and address bus is 32-bit. It could address 4 GB of memory. Could execute 110 million instructions per second. Cache memory: 8 KB for instructions. 8 KB for data. INTEL PENTIUM II Introduced in 1997. It was also 32-bit μP. Its clock speed was 233 MHz to 500 MHz. Could execute 333 million instructions per second. MMX technology was supported. L2 cache & processor were on one circuit.
FUNCTIONAL DIAGRAM OF 8086
- It is 16-bit microprocessor
- It has 20 bit address bus and can access up to 2^20 memory locations (1 MB).
- It can support up to 64K I/O ports.
- It provides 14, 16-bit registers
- It has multiplexed address and data bus AD0-AD15 & A16-A
- It requires single phase clock with 33% duty cycle to provide internal timing.
- Prefetches up to 6 instruction bytes from memory and queues them in order to speed up the processing. 8. It requires +5V supply
- 40 pin dual inline package
- 8086 supports 2 modes of operation a. Minimum mode b. Maximum mode a rich instruction set powerful interrupt structure Fetched instruction queue for overlapped fetching and execution etc. To improve the performance by implementing the parallel processing concept the CPU of the 8086 is divided into two independent sections. They are Bus Interface Unit (BIU) and Execution Unit (EU). The BIU sends out addresses, fetches instructions, read data from ports and memory and writes data to ports and memory. i.e the BIU handles all transfers of data and addresses on the buses
required by the Execution Unit whereas the Execution Unit tells the BIU where to fetch instructions or data from, decodes the instructions and executes the instructions. The BIU contains the circuit for physical address calculations a pre-decoding instruction byte queue (6 bytes long) four 16-bit segment registers (ES, CS, SS, DS) 16-bit instruction pointer (IP) The EU contains control circuitry, instruction decoder and ALU 16-bit flag registers four 16-bit general purpose registers (AX, BX, CX, DX) 16-bit pointer registers (SP, BP) and 16-bit index registers (SI, DI). Execution Unit: Control Circuitry, Instruction Decoder and ALU: The EU contains control circuitry which directs internal operations. A decoder in the EU translates instructions fetched from memory into a series of actions which the EU carries out. The EU has a 16-bit arithmetic logic unit which can add, subtract, AND, OR, XOR, increment, decrement, complement, or shift binary numbers.
Flag Registers: The 8086 16-bit flag register contents indicate the results of computations in the ALU. It also contains some flag bits to control the CPU operations. A flag is a flip-flop that indicates some condition produced by the execution of an instruction or controls certain operations of the EU. General Purpose Registers: General Registers : All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are: AX (Accumulator): This is accumulator register. It gets used in arithmetic, logic and data transfer instructions. In manipulation and division , one of the numbers involved must be in AX or AL. BX (Base Register): This is base register. BX register is an address register. It usually contain a data pointer used for based, based indexed or register indirect addressing. CX (Count register): This is Count register. This serves as a loop counter. Program loop constructions are facilitated by it. Count register can also be used as a counter in string manipulation and shift/rotate instruction. DX (Data Register): This is data register. Data register can be used as a port number in I/O operations. It is also used in multiplication and division. SP (Stack Pointer): This is stack pointer register pointing to program stack. It is used in conjunction with SS for accessing the stack segment. BP (Base Pointer): This is base pointer register pointing to data in stack segment. Unlike SP, we can use BP to access data in the other segments.
General purpose registers: There are four 16-bit 4 general purpose registers namely (AH, AL);(BH,BL); (CH,CL); (and DH,DL) which are part of Execution unit. These registers can be used individually for storing 16-bit data temporarily .The AL register is also called the accumulator. The pairs of registers can be used together to store 16-bit data words. It is always advantageous to store the data in these registers because the data can be accessed much more easily as these registers are already in the execution unit. Here L indicates the lower byte and H indicates the higher byte. X indicates the extended register. The general purpose data registers are used for data manipulations. The use of these registers is more dependent on the mode of addressing also. The other four registers of EU are referred to as index / pointer registers. They are Stack Pointer register, Base Pointer register, Source Index register and Destination Index registers. The pointer registers contain the offset within a particular segment.
The BP & SP registers holds the offsets within the data and stack segments respectively. The Index registers are used as general purpose registers as well as for holding the offset in case of indexed based and relative indexed addressing modes. The source Index register is generally used to store the offset of source data in data segment while the Destination Index register used to store the offset of destination in data or extra segment. These index registers are specifically used in string manipulations. Segment Registers : There are four 16 - bit segment registers namely code segment register(CS),Stack segment register(SS),Data segment register(DS) and Extra segment register(ES).The code segment register is used for addressing the 64kB memory location in the code segment of the memory ,where the code of the executable program is stored. Similarly the DS register points to the data segment of the 64kB memory where the data is stored. The Extra segment register also refers to essentially another data segment of the memory space. The SS register is useful for addressing stack segment of memory. So, the CS, DS, SS and ES segment registers respectively contains the segment addresses for the code, data, stack and extra segments of the memory. Instruction Pointer Register: It is a 16-bit register which always points to the next instruction to be executed within the currently executing code segment. So, this register contains the 16-bit offset address pointing to the next instruction code within the 64kB of the code segment area. Its content is automatically incremented as the execution of the next instruction takes place. Flag Register: This register is also called status register. It is a 16 bit register which contains six status flags and three control flags. So, only nine bits of the 16 bit register are defined and the remaining seven bits are undefined. Normally this status flag bits indicate the status of the ALU after the arithmetic or logical operations. Each bit of the status register is a flip/flop. The Flag register contains Carry flag, Parity flag; Auxiliary flag Zero flag, Sign flag, Trap flag, Interrupt flag, Direction flag and overflow flag as shown in the diagram. The CF, PF, AF, ZF, SF, OF are the status flags and the TF, IF and CF are the control flags.
CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction. PF - Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1’s else (for odd number of 1s) set to zero. AF- Auxiliary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during addition, or borrow for the lowest nibble, i.e, bit three, during subtraction. ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous instruction is zero.
PROGRAMMING MODEL
The programming model of the 8086 is considered to be program visible because its registers are used during application programming and are specified by the instructions. Figure below illustrates the programming model of 8086 microprocessor. Some registers are general-purpose or multipurpose registers, while some have special purposes. The multipurpose registers include EAX, EBX, ECX, EDX, EBP, EDI, and ESI. These registers hold various data sizes (bytes, words, or double words) and are used for almost any purpose, as dictated by a program.
Multipurpose Registers EAX (accumulator) EAX is referenced as a 32-bit register (EAX), as a 16-bit register (AX), or as either of two 8-bit registers (AH and AL).
EBX (base index) EBX is addressable as EBX, BX, BH, or BL. The BX register sometimes holds the offset address of a location in the memory system in all versions of the microprocessor. In the 80386 and above, EBX also can address memory data.
ECX (count) ECX is a general-purpose register that also holds the count for various instructions.
EDX (data) EDX is a general-purpose register that holds a part of the result from a multiplication or part of the dividend before a division. In the 80386 and above, this register can also address memory data.
EBP (base pointer) EBP points to a memory location in all versions of the micropro cessor for memory data transfers. This register is addressed as either BP or EBP.
EDI (destination index) EDI often addresses string destination data for the string instruc tions. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose register.
ESI (source index) ESI is used as either ESI or SI. The source index register often addresses source string data for the string instructions.
Special-purpose Registers.
The special-purpose registers include EIP, ESP, EFLAGS; and the segment registers CS, DS, ES, SS, FS, and GS. EIP (instruction pointer) EIP addresses the next instruction in a section of memory defined as a code segment.
ESP (stack pointer) ESP addresses an area of memory called the stack. The stack memory stores data through this pointer.
EFLAGS EFLAGS indicate the condition of the microprocessor and control its operation. The 8086- contain a FLAG register (16 bits) and the 80386 and above contain an EFLAG register (32-bit extended flag register).
C (carry) Carry holds the carry after addition or the borrow after subtraction. The carry flag also indicates error conditions, as dictated by some programs and procedures. This is especially true of the DOS function calls.
P (parity) Parity is a logic 0 for odd parity and a logic 1 for even parity. Parity is a count of ones in a number expressed as even or odd.
AC (alignment check) The alignment check flag bit activates if a word or doubleword is addressed on a non-word or non-doubleword boundary.
VIF (virtual interrupt flag) The VIF is a copy of the interrupt flag bit available to the Pentium-Pentium II microprocessors.
VIP (virtual interrupt pending) VIP provides information about a virtual mode interrupt for the Pentium—Pentium II microprocessors.
ID (identification) The ID flag indicates that the Pentium—Pentium II microprocessors support the CPUID instruction. Segment Registers Additional registers, called segment registers, generate memory addresses when combined with other registers in the microprocessor. Following is a list of each segment register, along with its function in the system: CS (code) The code segment is a section of memory that holds the code used by the microprocessor. The code segment register defines the starting address of the section of memory holding code.
DS (data) The data segment is a section of memory that contains most data used by a program.
ES (extra) The extra segment is an additional data segment that is used by some of the string instructions to hold destination data.
SS (stack) The stack segment defines the area of memory used for the stack.
FS and GS The FS and GS segments are supplemental segment registers available in the 80386, 80486, Pentium and Pentium Pro microprocessors to allow two additional memory segments for access by programs.
MEMORY ADDRESSING
PHYSICAL MEMORY ORGANIZATION
The 8086’s 1Mbyte memory address space is divided in to two independent 512Kbyte banks: the low (even) bank and the high (odd) bank. Data bytes associated with an even address (0000016, 0000216, etc.) reside in the low bank, and those with odd addresses (0000116, 0000316, etc.) reside in the high bank.
Address bits A1 through A19 select the storage location that is to be accessed. They are applied to both banks in parallel. A0and bank high enable (BHE) are used as bank-select signals.
The four different cases that happen during accessing data: Case 1: When a byte of data at an even address (such as X) is to be accessed:
8086 Pin diagram A16/S3, A17/S4, A18/S5, A19/S6: The specified address lines are multiplexed with corresponding status signals.
BHE (Active Low)/S7 (Output) : Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.
RD (Read) (Active Low) : The signal is used for read operation. It is an output signal. It is active when low.
READY: This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. The signal is active high.
INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized.
NMI (Input) – NON-MASKABLE INTERRUPT: It is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not mask able internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.
INTA: INTA: Interrupt acknowledges. It is active LOW during T2, T 3 and T w of each interrupt acknowledge cycle.
MN/ MX MINIMUM / MAXIMUM: This pin signal indicates what mode the processor is to operate in.
RQ/GT RQ/GT0: REQUEST/GRANT: These pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional with RQ/GT having higher priority than RQ /GT1.
LOCK: It’s an active low pin. It indicates that other system bus masters are not to allowed to gain control of the system bus while LOCK is active LOW. The LOCK signal remains active until the completion of the next instruction.
TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.
CLK- Clock Input: The clock input provides the basic timing for processor operation and bus control activity. It’s an asymmetric square wave with 33% duty cycle.
RESET (Input) : RESET: causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles.
Vcc – Power Supply ( +5V D.C.)
GND – Ground
QS1, QS0 (Queue Status) These signals indicate the status of the internal 8086 instruction queue according to the table shown below
