MULTICYCLE PATH
Definition of multicycle paths: By definition, a multi-cycle path is one in
which data launched from one flop is allowed (through architecture definition)
to take more than one clock cycle to reach to the destination flop. And it is
architecturally ensured either by gating the data or clock from reaching the
destination flops. There can be many such scenarios inside a System on Chip
where we can apply multi-cycle paths as discussed later. In this post, we
discuss architectural aspects of multicycle paths. For timing aspects like
application, analysis etc, please refer Multicycle paths handling in STA.
Why multi-cycle paths are introduced in designs: A typical System on Chip
consists of many components working in tandem. Each of these works on
different frequencies depending upon performance and other requirements.
Ideally, the designer would want the maximum throughput possible from each
component in design with paying proper respect to power, timing and area
constraints. The designer may think to introduce multi-cycle paths in the
design in one of the following scenarios:
1) Very large data-path limiting the frequency of entire component: Let
us take a hypothetical case in which one of the components is to be designed
to work at 500 MHz; however, one of the data-paths is too large to work at this
frequency. Let us say, minimum the data-path under consideration can take is
3 ns. Thus, if we assume all the paths as single cycle, the component cannot
work at more than 333 MHz; however, if we ignore this path, the rest of the
design can attain 500 MHz without much difficulty. Thus, we can sacrifice this
path only so that the rest of the component will work at 500 MHz. In that case,
we can make that particular path as a multi-cycle path so that it will work at
250 MHz sacrificing the performance for that one path only.
2) Paths starting from slow clock and ending at fast clock: For simplicity,
let us suppose there is a data-path involving one start-point and one end point
with the start-point receiving clock that is half in frequency to that of the end
point. Now, the start-point can only send the data at half the rate than the end
point can receive. Therefore, there is no gain in running the end-point at
