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PRELAB 7
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Modulo10_Counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; CountEnable : in STD_LOGIC; UpDown : in STD_LOGIC; Count : out STD_LOGIC_VECTOR(3 downto 0) ); end Modulo10_Counter; architecture Behavioral of Modulo10_Counter is signal state : STD_LOGIC_VECTOR(3 downto 0) := "0000"; begin process(Clock, Reset) begin if Reset = '0' then state <= "0000"; -- Reset to 0 elsif rising_edge(Clock) then if CountEnable = '1' then if UpDown = '1' then -- Count Up case state is when "1001" => state <= "0000"; -- Wrap around
when others => state <= state + 1; end case; else -- Count Down case state is when "0000" => state <= "1001"; -- Wrap around when others => state <= state - 1; end case; end if; end if; end if; end process; Count <= state; end Behavioral; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY lab7 IS PORT(udn, CLOCK, RESETN, CE : IN STD_LOGIC; HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END lab7; ARCHITECTURE behavior of lab7 IS TYPE STATETYPE IS (COUNT0, COUNT1, COUNT2, COUNT3, COUNT4, COUNT5, COUNT6, COUNT7, COUNT8, COUNT9); SIGNAL STATE : STATETYPE;
state<=count0; when "01" => state<=count0; when "10" => state<=count9; when "11" => state<=count1; end case; when count1 => case ce_udn is when "00" => state<=count1; when "01" => state<=count1; when "10" => state<=count0; when "11" => state<=count2; end case; when count2 =>
case ce_udn is when "00" => state<=count2; when "01" => state<=count2; when "10" => state<=count1; when "11" => state<=count3; end case; when count3 => case ce_udn is when "00" => state<=count3; when "01" => state<=count3; when "10" => state<=count2; when "11" => state<=count4;
when "11" => state<=count6; end case; when count6 => case ce_udn is when "00" => state<=count6; when "01" => state<=count6; when "10" => state<=count5; when "11" => state<=count7; end case; when count7 => case ce_udn is when "00" => state<=count7; when "01" => state<=count7;
when "10" => state<=count6; when "11" => state<=count8; end case; when count8 => case ce_udn is when "00" => state<=count8; when "01" => state<=count8; when "10" => state<=count7; when "11" => state<=count9; end case; when count9 => case ce_udn is when "00" =>
