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Computer Architecture Mid-Semester Examination: Exercises and Questions, Exams of Computer Architecture and Organization

it is a Previous year question paper

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2021/2022

Uploaded on 10/02/2023

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Motilal
Nehru
National
Institute
of
Technology
Allahabad,
Prayagraj
Computer
Science
&
Engineering
Department
Mid-Semester
Examination
2022
Programme
Name:
B.Tech
Semester:
5th
Course Code:
CS
15106
Course
Name:
Computer
Architecture
Branch:
(Computer
Sc.&
Engg.)
Student
Reg.No.:2
o 2
04
OL
Duration:
90
Minutes
Max.
Marks:
20
Instruetions:
(Related
to
Questions)
1.
Attempt
all
questions.
2.
All
parts
of
a
question
should
be
answered
in
one
attempt
SEQUENTIALLY.
3. Make &
State
necessary
Assumptions
(if
any)
clearly.
Marks
You
have a
system
that contains a
special
processor for
doing
floating-point
operations.
You
have
04
determined
that
60%
of your
computations
can
use
the
floating-point
processor. When a
program
uses
the
floating-point
processor,
the
speedup
of
the
floating-point
processor
is
40%
faster than
when
it
does not
use
it.
Q1
(i)
Calculate
overall
speedup
by
using
the
floating-point
processor.
(i)
In
order
to
improve
the
speedup
consider
two
options:
Option
1:
Modify
the
compiler
so
that
70%
of the
computations
can
use
the
floating
point
processor. Cost
of
this
option
is
$50K.
Option
2:
Modify
the
floating-point
processor. The
speedup
of
the
floating-point
processor
is
100%
faster than when
it
does
not
use
it.
Assume
in
this
case
that
50%
of
the
Computations
can
use
the
floating-point
processor. Cost of this
option
is
$60K.
Which
option
would you
recommend?
Justify
your
answer
quantitatively.
Q2
Consider
the
following
code
executing
on
general
architecture without
pipelined.
Use the
loop
06
unrolling
5 times.
What
is
the average tlock
cycle
per
iteration?
1
Loop:
L.D
FO,0(R1)
FO=vector
element
2 stall
3
ADD.D
F4,
FO,
F2
add scalar
in
F2
stall
stall
S.D
O(R1),F4
store
result
DSUBUIR1,R1,8
decrement pointer
8B
(DW)
8
BNEZ
R1,
Loop
branch R1!=zero
stall
delayed
branch
slot
Or
Write
short
notes
on
the
following:
a
Compiler
based Static
Scheduling
Vs
Hardware based
Dynamic
Scheduling
b)
Dynamic
branch
prediction
c)
Unknown
dependency
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of
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Download Computer Architecture Mid-Semester Examination: Exercises and Questions and more Exams Computer Architecture and Organization in PDF only on Docsity!

Motilal

Nehru

National

Institute

of

Technology

Allahabad,

Prayagraj

Computer Science

Engineering

Department

Mid-Semester Examination 2022

Programme Name: B.Tech

Semester: 5th

Course

Code:

CS

Course

Name:

Computer

Architecture

Branch:

(Computer

Sc.&

Engg.)

Student

Reg.No.:

o

OL

Duration: 90 Minutes

Max. Marks: 20

Instruetions:

(Related

to

Questions)

Attempt

all

questions.

All

parts

of a

question

should be

answered

in

one

attempt

SEQUENTIALLY.

Make

State

necessary

Assumptions (if

any)

clearly.

Marks

You have a

system

that

contains a

special

processor

for

doing

floating-point operations. You have

determined that

of your computations can use the

floating-point

processor.

When a

program

uses the

floating-point

processor, the

speedup

of the

floating-point

processor

is 40% faster than

when it does not use it.

Q

(i) Calculate

overall

speedup

by

using

the

floating-point

processor.

(i)

In order to

improve

the

speedup consider two

options:

Option

1:

Modify

the

compiler

so that 70%

of the

computations can use the

floating

point

processor. Cost of this

option

is

$50K.

Option

2:

Modify

the

floating-point

processor.

The

speedup of the

processor floating-point is

faster than

when it does not use it. Assume in this case that 50% of the

Computations

can use the floating-point

processor.

Cost of this

option

is

$60K.

Which

option would

you recommend?

Justify your

answer

quantitatively.

Q

Consider

the

following

code

executing

on

general architecture

without

pipelined.

Use the

loop

unrolling

5 times. What is the average tlock

cycle

per

iteration?

1 Loop: L.D

FO,0(R1) FO=vector element

2

stall

3 ADD.D F4, FO, F add scalar in F

stall

stall

S.D

O(R1),F4 store result

DSUBUIR1,R1,8 decrement

pointer

8B

(DW)

8 BNEZ R1,

Loop branch R1!=zero

stall

delayed branch slot

Or

Write

short notes on

the following:

a Compiler

based

Static

Scheduling

Vs Hardware based

Dynamic

Scheduling

b)

Dynamic branch

prediction c) Unknown dependency

Page 1 of 2

05

Q3 Consider the

execution of the

following

code

segment:

ADD.D F1, F2, F

MULD FS, F1, F
DIV.D F4, F10, F
MUL.D F7, F8, F

Executed

on a

processOs

which

uses

Tomasulo's

algorithm

to

dynamically schedule

instructions

(single

issue per

cycle

  • no

speculation) with the

following

non-pipelined execution units:

A

2-cycle,

FP add

unit,

A

3-cycle,

FP

multiply

unit

A 6-cycle, FP divide unit

Trace the

execution

by

showing

the

instruction

status,

the

reservation

station status and

register

status

indicator at

the end of

cycles 3,

12 and 15. Assume that two

reservation

stations are

used for each

functional unit

(add1, add2,

mult1,

mult2, div1,

div2).

Consider the

following

sequence

of

instructions.

Q

Instructioon

Instruction

Number

| SUBDFA)F4, F

ADDD F6, F3,F

DIVD F3FF

MULTD F1,F6, F

DIVDF5)

F9,

F

ADDUF2,5, F

ADDD F8, F1, F

a Draw the

dependency graph

for the

above

instructions and

indicate the

type

of data dependency for each edge.

b Assuming

that you have as

many functional

units as

you need,

list all

possible

valid

instruction

sequences

and also

compute

average software

parallelism?

Page 2 of 2