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5 problems, 5 pages Final Exam Solutions 14 December 2001
Problem 1 (2 parts, 20 points) Datapath Elements
Part A (10 points) Using only pass gates and inverters, design a four to one multiplexer (i.e., a logical unit). Label the inputs I 0 , I 1 , I 2 , I 3 , S 1 , and S 0. Label the output Out. For a clearer picture, only attach the control signal for the active high control input of the pass gates.
Part B (10 points) Implement a four bit logical shifter that can shift one bit left or right using 2 to 1 multiplexers (do not implement the MUX). The inputs are I 0 , I 1 , I 2 , I 3 , and right/-left. The outputs are O 0 , O 1 , O 2 , and O 3. Be sure to label all inputs on the mux including S , I (^0) , and I 1.
I3 I2 I1 I
right
-left
O3 O2 O1 O
SI 1 I^0 SI 1 I^0 SI^1 I^0 SI^1 I^0
5 problems, 5 pages Final Exam Solutions 14 December 2001
Problem 2 (5 parts, 50 points) Assembly Language Consider the following MIPS program fragment. The instruction set is listed below.
address label instruction 1000 slt $2, $3, $ 1004 bne $2, $0, skip 1008 jal factorial 1012 lui $3, 0xF64D 1016 ori $3, $3, 0x0DAD 1020 sw $2, ($3) 1024 skip1: j break Part A (10 points) What is the branch offset (in bytes) for the bne instruction?
branch offset (in bytes): 4 instructions x 4 bytes/instruction = 16 bytes Part B (10 points) For what values of $3 will subroutine factorial be called?
values of $3 (in decimal): $3 greater or equal to zero Part C (10 points) What does $31 contains when subroutine factorial begins execution?
contents of $31 (in decimal): 1012 Part D (10 points) What does $3 contain when the ori instruction completes?
contents of $3 (in hexadecimal): F64D0DAD Part E (10 points) Looking at the entire fragment, describe the likely purpose of sw instruction?
The sw instruction stores the result of factorial at memory location F64D0DAD instruction example meaning add add $1,$2,$3 $1 = $2 + $ subtract sub $1,$2,$3 $1 = $2 - $ add immediate addi $1,$2,100 $1 = $2 + 100 multiply mul $1,$2,$3 $1 = $2 * $ divide div $1,$2,$3 $1 = $2 / $ and and $1,$2,$3 $1 = $2 & $ or or $1,$2,$3 $1 = $2 | $ and immediate andi $1,$2,100 $1 = $2 & 100 or immediate ori $1,$2,100 $1 = $2 | 100 shift left logical sll $1,$2,5 $1 = $2 << 5 shift right logical srl $1,$2,5 $1 = $2 >> 5 load word lw $1, ($2) $1 = memory [$2] store word sw $1, ($2) memory [$2] = $ load upper immediate lui $1,100 (^) $1 = 100 x 2 16 branch if equal beq $1,$2,100 if ($1 = $2), PC = PC + 4 + 100 branch if not equal bne $1,$2,100 (^) if ($1 ≠ $2), PC = PC + 4 + 100 set if less than slt $1, $2, $3 if ($2 < $3), $1 = 1 else $1 = 0 set if less than immediate slti $1, $2, 100 if ($2 < 100), $1 = 1 else $1 = 0 jump j 10000 PC = 10000 jump register jr $31 PC = $ jump and link jal 10000 $31 = PC + 4; PC = 10000
5 problems, 5 pages Final Exam Solutions 14 December 2001
Problem 4 (2 parts, 20 points) Adder/ Subtractor
Part A (10 points) The adder below adds two four bit numbers A and B and produces a four bit result S. Add extra digital logic to support subtraction as well as addition. Label inputs X 3 , X 2 ,
X 1 , X 0 , Y 3 , Y 2 , Y 1 , Y 0 , ADD / SUB and outputs Z 3 , Z 2 , Z 1 , Z 0. Do not consider error determination here.
Part B (10 points) Consider a function that determines whether an error occurred when adding or subtracting two two’s complement numbers. Suppose XMSB and YMSB are the most significant bits of the two numbers being processed and ZMSB is the most significant bit of the result. Complete the truth table below to indicate an error (Err) when one has occurred.
Addition (X+Y=Z) Subtraction (X-Y=Z) XMSB YMSB ZMSB Err XMSB YMSB ZMSB Err 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 1 1 1 0 1 1 1 0
5 problems, 5 pages Final Exam Solutions 14 December 2001
Problem 5 (3 parts, 30 points) Memory Systems
This problem examines a 1 Gbit DRAM chip organized as 128 million addresses of 8-bit words.
Part A (10 points) Draw an DRAM memory cell. Label the signals D and Select.
select
D
Part B (10 points) Suppose both the DRAM cell and the DRAM chip are square. Using the organization approach discussed in class, answer the following questions about the chip.
number of columns (^2 30) = 215 = 32 K
number of words per column 215 / 2 3 = 2^12 = 4K column decoder required ( n to m ) 15 to 32K
type of mux required 4K to 1
Part C (10 points) Consider a 1 billion address by 128-bit words DRAM memory system designed to be a solid state disk.
number of chips needed in one bank 128/8 = 2^7 /2^3 = 2^4 = 16
number of banks for memory system 1B/128M = 2^30 /2^27 = 2^3 = 8 memory decoder required ( n to m ) 3 to 8 number of DRAM chips required 8 x 16 = 2^3 x 2^4 = 2^7 = 128
