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System level design of digital logic circuits using hardwired and programmable logic devices. ROMs, PROMs, and PLAs. Synchronous and asynchronous circuit design and analysis.
Typology: Lecture notes
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PROGRAMMABLE LOGIC DEVICES
With fixed logic devices, the time required to go fromdesign, to prototypes, to a final manufacturing runcan take from several months to more than a year,depending on the complexity of the device.
PROGRAMMABLE LOGIC DEVICES
If the device does not work properly, or if therequirements change, a new design must bedeveloped.
With PLDs, designers use inexpensive software tools to quickly develop, simulate, and test theirdesigns.
Then, a design can be quickly programmed into adevice, and immediately tested in a live circuit.
PROGRAMMABLE LOGIC DEVICES
Simple Programmable Logic Devices (
s),
Complex Programmable Logic Devices (
s)
Field Programmable Gate Arrays (
s)
Field Programmable InterConnect (
s)
PROGRAMMABLE LOGIC DEVICES
ROM (Read Only Memory)
PLA (Programmable Logic Array)
PAL (Programmable Array Logic)
GAL (Generic Array Logic)
SPLDs are the smallest and consequently the least-expensive formof Programmable logic.
An SPLD is typically comprised of four to 22 macrocells
and can
typically replace a few 7400-series TTL devices.
Each of the macrocells
is typically fully connected to the others in
the device.
Most SPLDs use either fuses
or non-volatile memory cells
such as
EPROM
, EEPROM
, to define the functionality.
PROGRAMMABLE LOGIC DEVICES
Conventional Symbol
Array Logic Symbol(If
x
is not present, then there is no
connection)
PROGRAMMABLE LOGIC DEVICES
PROGRAMMABLE LOGIC DEVICES
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PROGRAMMABLE LOGIC DEVICES
PROGRAMMABLE LOGIC DEVICES
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PROGRAMMABLE LOGIC DEVICES
Programmable Logic
restricted to a particular function.
It may be
at
different points of the life cycle.
At the earliest, it is programmed
by the semiconductor vendor (standard cell, gate array), by thedesigner prior to assembly, or by the user, in circuit.
Gate Array
dimensional array to form the standard base of an applicationspecific integrated circuit (ASIC).
The devices is programmed by
custom metal layers interconnecting nodes in the array.
Some
gate arrays have other features such as SRAM blocks, phase lockloops, delay locked loops, etc.
Standard Cell
cell may be different and optimized for each "standard"function.
There are no standard layers to the device and each
PROGRAMMABLE LOGIC DEVICES
Programmable Read Only Memory (PROM
) - This device has
a fixed, fully decoded AND plane and a programmable ORplane.
The programmable element for these devices include
EPROM, EEPROM, fuses and antifuses.
Fuse materials include
nichrome and polysilicon elements.
Antifuse structures may
consist of Oxide-Nitride-Oxide (Lockheed-Martin) or amorphoussilicon (UTMC) material.
Other elements are possible and may be
used in some devices.
Programmed Array Logic (PAL)
programmable AND plane and a fixed OR plane.
Many
commercial/military devices use fuses - one device family usesEEPROM cells and logic (CoolRunner).
Programmable Logic Array (PLA)
programmable AND and OR planes.
PLA structures may also
appear as part of some CPLDs.
Complex Programmable Logic Device (CPLD)
density programmable device generally based on the PALarchitecture.
The routing structure leads to more predictable
timing than the FPGA.
PROGRAMMABLE LOGIC DEVICES
k 2 x n ROM
k^
inputs (addresses)
n outputs (data)
PROGRAMMABLE LOGIC DEVICES
PROGRAMMABLE LOGIC DEVICES
