82C55A Microcontroller Pinouts and Operating Modes, Study notes of Microprocessors

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CECS 347

LECTURE 4

82C55 PROGRAMMABLE PERIPHERAL

INTERFACE

June 1998

CMOS Programmable

Peripheral Interface

Features

• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and

8MHz 80C86 and 80C

• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB)................ .10μA

Description

The Intersil 82C55A is a high performance CMOS version of

the industry standard 8255A and is manufactured using a

self-aligned silicon gate CMOS process (Scaled SAJI IV). It

is a general purpose programmable I/O device which may be

used with many different microprocessors. There are 24 I/O

pins which may be individually programmed in 2 groups of

12 and used in 3 major modes of operation. The high

performance and industry standard configuration of the

82C55A make it compatible with the 80C86, 80C88 and

other microprocessors.

Static CMOS circuit design insures low operating power. TTL

compatibility over the full military temperature range and bus

hold circuitry eliminate the need for pull-up resistors. The

Intersil advanced SAJI process results in performance equal

to or greater than existing functionally equivalent products at

Ordering Information a fraction of the power.

PART NUMBERS

PACKAGE

TEMPERATURE

RANGE

PKG.

5MHz 8MHz NO.

CP82C55A-5 CP82C55A

40 Ld PDIP

0 oC to 70oC E40.

IP82C55A-5 IP82C55A -40oC to 85oC E40.

CS82C55A-5 CS82C55A

44 Ld PLCC

0 oC to 70oC N44.

IS82C55A-5 IS82C55A -40oC to 85oC N44.

CD82C55A-5 CD82C55A

40 Ld

CERDIP

0 oC to 70oC F40.

ID82C55A-5 ID82C55A -40oC to 85oC F40.

MD82C55A-5/B MD82C55A/B -55oC to 125oC F40.

8406601QA 8406602QA SMD# F40.

MR82C55A-5/B MR82C55A/B

44 Pad

CLCC

-55oC to 125oC J44.A

8406601XA 8406602XA SMD# J44.A

Pinouts

82C55A (DIP)

TOP VIEW

82C55A (CLCC)

TOP VIEW

82C55A (PLCC)

TOP VIEW

PA

PA

PA

PA

RD

CS

GND

A

A

PC

PC

PC

PC

PC

PC

PC

PC

PB

PB

PB

PA

PA

PA

PA

WR

RESET

D

D

D

D

D

D

D

D

VCC

PB

PB

PB

PB

PB

GND

NC

A

A

PC

PC

PC

PC

PC

PC

PC

PC3PB0PB1PB2PB3PB4PB5PB6PB7VCCNC

NC

RESET

D

D

D

D

D

D

D

D

NC

CSRDPA0PA1PA2PA3PA4PA5PA6PA7WR

CS

GND

A

A

PC

PC

PC

PC

PC

PC

PC3PB0PB1PB2NCPB3PB4PB5PB6PB

NC

RESET

D

D

D

D

D

D

D

D

VCC

RDPA0PA1PA2PA3NCPA4PA5PA6PA7WR

PC

NC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 2969.

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

Functional Description

Data Bus Buffer

This three-state bi-directional 8-bit buffer is used to interface

the 82C55A to the system data bus. Data is transmitted or

received by the buffer upon execution of input or output

instructions by the CPU. Control words and status informa-

tion are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and

external transfers of both Data and Control or Status words.

It accepts inputs from the CPU Address and Control busses

and in turn, issues commands to both of the Control Groups.

(CS) Chip Select. A “low” on this input pin enables the

communcation between the 82C55A and the CPU.

(RD) Read. A “low” on this input pin enables 82C55A to send

the data or status information to the CPU on the data bus. In

essence, it allows the CPU to “read from” the 82C55A.

(WR) Write. A “low” on this input pin enables the CPU to

write data or control words into the 82C55A.

(A0 and A1) Port Select 0 and Port Select 1. These input

signals, in conjunction with the RD and WR inputs, control

the selection of one of the three ports or the control word

register. They are normally connected to the least significant

bits of the address bus (A0 and A1).

(RESET) Reset. A “high” on this input initializes the control

register to 9Bh and all ports (A, B, C) are set to the input

mode. “Bus hold” devices internal to the 82C55A will hold

the I/O port inputs to a logic “1” state with a maximum hold

current of 400μA.

Group A and Group B Controls

The functional configuration of each port is programmed by

the systems software. In essence, the CPU “outputs” a con-

trol word to the 82C55A. The control word contains

information such as “mode”, “bit set”, “bit reset”, etc., that ini-

tializes the functional configuration of the 82C55A.

Each of the Control blocks (Group A and Group B) accepts

“commands” from the Read/Write Control logic, receives

“control words” from the internal data bus and issues the

proper commands to its associated ports.

Control Group A - Port A and Port C upper (C7 - C4)

Control Group B - Port B and Port C lower (C3 - C0)

The control word register can be both written and read as

shown in the “Basic Operation” table. Figure 4 shows the

control word format for both Read and Write operations.

When the control word is read, bit D7 will always be a logic

“1”, as this implies control word mode information.

82C55A BASIC OPERATION

A1 A0 RD WR CS

INPUT OPERATION

(READ)

0 0 0 1 0 Port A → Data Bus

0 1 0 1 0 Port B → Data Bus

1 0 0 1 0 Port C → Data Bus

1 1 0 1 0 Control Word → Data Bus

OUTPUT OPERATION

(WRITE)

0 0 1 0 0 Data Bus → Port A

0 1 1 0 0 Data Bus → Port B

1 0 1 0 0 Data Bus → Port C

1 1 1 0 0 Data Bus → Control

DISABLE FUNCTION

X X X X 1 Data Bus → Three-State

X X 1 1 0 Data Bus → Three-State

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

READ/WRITE, GROUP A & B CONTROL LOGIC

FUNCTIONS

GROUP A

PORT A

GROUP A

PORT C

UPPER

GROUP B

PORT C

LOWER

GROUP B

PORT B

GROUP B

CONTROL

GROUP A

CONTROL

DATA

READ

WRITE

CONTROL

LOGIC

RD

WR

A

A

RESET

CS

D7-D

POWER

SUPPLIES

+5V

GND

BI-DIRECTIONAL

DATA BUS

I/O

PA7-

I/O

PC7-

I/O

PC3-

I/O

PB7-

BUFFER

BUS

PB

PC

PC

PA

8-BIT

INTERNAL

DATA BUS

Ports A, B, and C

The 82C55A contains three 8-bit ports (A, B, and C). All can

be configured to a wide variety of functional characteristics

by the system software but each has its own special features

or “personality” to further enhance the power and flexibility of

the 82C55A.

Port A One 8-bit data output latch/buffer and one 8-bit data

input latch. Both “pull-up” and “pull-down” bus-hold devices

are present on Port A. See Figure 2A.

Port B One 8-bit data input/output latch/buffer and one 8-bit

data input buffer. See Figure 2B.

Port C One 8-bit data output latch/buffer and one 8-bit data

input buffer (no latch for input). This port can be divided into

two 4-bit ports under the mode control. Each 4-bit port con-

tains a 4-bit latch and it can be used for the control signal

output and status signal inputs in conjunction with ports A

and B. See Figure 2B.

Operational Description

Mode Selection

There are three basic modes of operation than can be

selected by the system software:

Mode 0 - Basic Input/Output

Mode 1 - Strobed Input/Output

Mode 2 - Bi-directional Bus

When the reset input goes “high”, all ports will be set to the

input mode with all 24 port lines held at a logic “one” level by

internal bus hold devices. After the reset is removed, the

82C55A can remain in the input mode with no additional ini-

tialization required. This eliminates the need to pullup or pull-

down resistors in all-CMOS designs. The control word

register will contain 9Bh. During the execution of the system

program, any of the other modes may be selected using a

single output instruction. This allows a single 82C55A to

service a variety of peripheral devices with a simple software

maintenance routine. Any port programmed as an output

port is initialized to all zeros when the control word is written.

FIGURE 2A. PORT A BUS-HOLD CONFIGURATION

FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION

FIGURE 2. BUS-HOLD CONFIGURATION

MASTER

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

EXTERNAL

PORT A PIN

OUTPUT MODE

INPUT MODE

RESET

OR MODE

CHANGE

INTERNAL

DATA IN

INTERNAL

DATA OUT

(LATCHED)

EXTERNAL

PORT B, C

OUTPUT MODE

PIN

P

VCC

FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE

DATA BUS

8 I/O

B

PB7-PB

4 I/O

PC3-PC

4 I/O

C

PC7-PC

8 I/O

A

PA7-PA

CONTROL BUS

ADDRESS BUS

RD, WR

82C55A

D7-D0 A0-A

CS

MODE 0

8 I/O

B

PB7-PB0 CONTROL

C

8 I/O

A

PA7-PA

MODE 1

OR I/O

CONTROL

OR I/O

8 I/O

B

PB7-PB

C

BI-

A

PA7-PA

MODE 2

CONTROL

DIRECTIONAL

FIGURE 4. MODE DEFINITION FORMAT

D7 D6 D5 D4 D3 D2 D1 D

PORT C (LOWER)

1 = INPUT

0 = OUTPUT

PORT B

1 = INPUT

0 = OUTPUT

MODE SELECTION

0 = MODE 0

1 = MODE 1

GROUP B

PORT C (UPPER)

1 = INPUT

0 = OUTPUT

PORT A

1 = INPUT

0 = OUTPUT

MODE SELECTION

00 = MODE 0

01 = MODE 1

GROUP A

1X = MODE 2

MODE SET FLAG

1 = ACTIVE

CONTROL WORD

Mode 0 (Basic Input)

Mode 0 (Basic Output)

Mode 0 Configurations

CONTROL WORD #0 CONTROL WORD

CONTROL WORD #1 CONTROL WORD

tRA

tHR

tRR

tIR

tAR

tRD tDF

RD

INPUT

CS, A1, A

D7-D

tAW (^) tWA

tWB

tWW

tDW tWD

WR

D7-D

CS, A1, A

OUTPUT

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

CONTROL WORD #4 CONTROL WORD

CONTROL WORD #5 CONTROL WORD

CONTROL WORD #6 CONTROL WORD

CONTROL WORD #7 CONTROL WORD

Mode 0 Configurations (Continued)

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

D

D

D

D

D

D

D

D

PA7 - PA

PC7 - PC

PC3 - PC

PB7 - PB

D7 - D

82C55A

A

B

C

INTR (Interrupt Request)

A “high” on this output can be used to interrupt the CPU

when and input device is requesting service. INTR is set by

the condition: STB is a “one”, IBF is a “one” and INTE is a

“one”. It is reset by the falling edge of RD. This procedure

allows an input device to request service from the CPU by

simply strobing its data into the port.

INTE A

Controlled by bit set/reset of PC4.

INTE B

Controlled by bit set/reset of PC2.

Output Control Signal Definition

(Figure 8 and 9)

OBF - Output Buffer Full F/F). The OBF output will go “low”

to indicate that the CPU has written data out to be specified

port. This does not mean valid data is sent out of the part at

this time since OBF can go true before data is available.

Data is guaranteed valid at the rising edge of OBF, (See

Note 1). The OBF F/F will be set by the rising edge of the

WR input and reset by ACK input being low.

ACK - Acknowledge Input). A “low” on this input informs the

82C55A that the data from Port A or Port B is ready to be

accepted. In essence, a response from the peripheral device

indicating that it is ready to accept data, (See Note 1).

INTR - (Interrupt Request). A “high” on this output can be

used to interrupt the CPU when an output device has

accepted data transmitted by the CPU. INTR is set when

ACK is a “one”, OBF is a “one” and INTE is a “one”. It is

reset by the falling edge of WR.

INTE A

Controlled by Bit Set/Reset of PC6.

INTE B

Controlled by Bit Set/Reset of PC2.

NOTE:

1. To strobe data into the peripheral device, the user must operate

the strobe line in a hand shaking mode. The user needs to send

OBF to the peripheral device, generates an ACK from the pe-

ripheral device and then latch data into the peripheral device on

the rising edge of OBF.

FIGURE 7. MODE 1 (STROBED INPUT)

tST

STB

INTR

RD

INPUT FROM

IBF

PERIPHERAL

tSIB

tSIT

tPH

tPS

tRIT

tRIB

FIGURE 8. MODE 1 OUTPUT

D

D

D

D

D3 D2 D1 D

CONTROL WORD

MODE 1 (PORT A)

PC

PC6 ACKA

PA7-PA

OBFA

PC3 INTRA

PC4, PC

WR^2

PC4, PC

1 = INPUT

0 = OUTPUT

D7 D6 D5 D4 D3 D2 D1 D

CONTROL WORD

MODE 1 (PORT B)

PC

INTE PC2 ACKB

B

PB7-PB

OBFB

PC0 INTRB

WR

INTE

A

Operating Modes

Mode 2 (Strobed Bi-Directional Bus I/O)

The functional configuration provides a means for communi-

cating with a peripheral device or structure on a single 8-bit

bus for both transmitting and receiving data (bi-directional

bus I/O). “Hand shaking” signals are provided to maintain

proper bus flow discipline similar to Mode 1. Interrupt gener-

ation and enable/disable functions are also available.

Mode 2 Basic Functional Definitions:

• Used in Group A only
• One 8-bit, bi-directional bus Port (Port A) and a 5-bit

control Port (Port C)

• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and

status for the 8-bit, bi-directional bus port (Port A)

Bi-Directional Bus I/O Control Signal Definition

(Figures 11, 12, 13, 14)

INTR - (Interrupt Request). A high on this output can be

used to interrupt the CPU for both input or output operations.

Output Operations

OBF - (Output Buffer Full). The OBF output will go “low” to

indicate that the CPU has written data out to port A.

ACK - (Acknowledge). A “low” on this input enables the

three-state output buffer of port A to send out the data. Oth-

erwise, the output buffer will be in the high impedance state.

INTE 1 - (The INTE flip-flop associated with OBF). Con-

trolled by bit set/reset of PC4.

Input Operations

STB - (Strobe Input). A “low” on this input loads data into the

input latch.

IBF - (Input Buffer Full F/F). A “high” on this output indicates

that data has been loaded into the input latch.

INTE 2 - (The INTE flip-flop associated with IBF). Controlled

by bit set/reset of PC4.

FIGURE 9. MODE 1 (STROBED OUTPUT)

tWOB

tWB

tAK tAIT

tAOB

tWIT

OBF

WR

INTR

ACK

OUTPUT

Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O

applications.

FIGURE 10. COMBINATIONS OF MODE 1

D

D

D

D

D3 D2 D1 D

CONTROL WORD

PORT A - (STROBED INPUT)

PC

OBFB

PA7-PA

STBA

PC0 INTRB

PC6, PC

WR

PC6, PC

1 = INPUT

0 = OUTPUT

PORT B - (STROBED OUTPUT)

PC5 IIBFA

PC3 INTRA

PC2 ACKB

I/O

PC

PB7, PB

RD

D

D

D

D

D3 D2 D1 D

CONTROL WORD

PORT A - (STROBED OUTPUT)

PC

STBB

PA7-PA

OBFA

PC0 INTRB

PC4, PC

RD

PC4, PC

1 = INPUT

0 = OUTPUT

PORT B - (STROBED INPUT)

PC6 ACKA

PC3 INTRA

PC1 IBFB

I/O

PC

PB7, PB

WR

MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT)

MODE 2 AND MODE 1 (OUTPUT) MODE 2 AND MODE 1 (INPUT)

FIGURE 14. MODE 2 COMBINATIONS

D

D6 D5 D4 D3 D2 D1 D

CONTROL WORD

PC

STBA

PA7-PA

OBFA

PC5 IBFA

PC2-PC

RD

PC2-PC

1 = INPUT

0 = OUTPUT

PC6 ACKA

PC3 INTRA

I/O

PC

PB7-PB

WR

D

D6 D5 D4 D3 D2 D1 D

CONTROL WORD

PC

STBA

PA7-PA

OBFA

PC5 IBFA

PC2-PC

RD

PC2-PC

1 = INPUT

0 = OUTPUT

PC6 ACKA

PC3 INTRA

I/O

PC

PB7, PB

WR

D

D6 D5 D4 D3 D2 D1 D

CONTROL WORD

PC

STBA

PA7-PA

OBFA

PC5 IBFA

RD

PC6 ACKA

PC3 INTRA

PC

PB7-PB

WR

PC1 OBFB

PC2 ACKB

PC0 INTRB

D

D6 D5 D4 D3 D2 D1 D

CONTROL WORD

PC

STBA

PA7-PA

OBFA

PC5 IBFA

RD

PC6 ACKA

PC3 INTRA

PC

PB7-PB

WR

PC2 STBB

PC

PC0 INTRB

IBFB

Special Mode Combination Considerations

There are several combinations of modes possible. For any

combination, some or all of Port C lines are used for control

or status. The remaining bits are either inputs or outputs as

defined by a “Set Mode” command.

During a read of Port C, the state of all the Port C lines,

except the ACK and STB lines, will be placed on the data

bus. In place of the ACK and STB line states, flag status will

appear on the data bus in the PC2, PC4, and PC6 bit

positions as illustrated by Figure 17.

Through a “Write Port C” command, only the Port C pins

programmed as outputs in a Mode 0 group can be written.

No other pins can be affected by a “Write Port C” command,

nor can the interrupt enable flags be accessed. To write to

any Port C output programmed as an output in Mode 1 group

or to change an interrupt enable flag, the “Set/Reset Port C

Bit” command must be used.

With a “Set/Reset Port Cea Bit” command, any Port C line

programmed as an output (including IBF and OBF) can be

written, or an interrupt enable flag can be either set or reset.

Port C lines programmed as inputs, including ACK and STB

lines, associated with Port C fare not affected by a

“Set/Reset Port C Bit” command. Writing to the correspond-

ing Port C bit positions of the ACK and STB lines with the

“Set Reset Port C Bit” command will affect the Group A and

Group B interrupt enable flags, as illustrated in Figure 17.

Current Drive Capability

Any output on Port A, B or C can sink or source 2.5mA. This

feature allows the 82C55A to directly drive Darlington type

drivers and high-voltage displays that require such sink or

source current.

MODE DEFINITION SUMMARY

MODE 0 MODE 1 MODE 2

IN OUT IN OUT GROUP A ONLY

PA

PA

PA

PA

PA

PA

PA

PA

In

In

In

In

In

In

In

In

Out

Out

Out

Out

Out

Out

Out

Out

In

In

In

In

In

In

In

In

Out

Out

Out

Out

Out

Out

Out

Out

PB

PB

PB

PB

PB

PB

PB

PB

In

In

In

In

In

In

In

In

Out

Out

Out

Out

Out

Out

Out

Out

In

In

In

In

In

In

In

In

Out

Out

Out

Out

Out

Out

Out

Out

PC

PC

PC

PC

PC

PC

PC

PC

In

In

In

In

In

In

In

In

Out

Out

Out

Out

Out

Out

Out

Out

INTRB

IBFB

STBB

INTRA

STBA

IBFA

I/O

I/O

INTRB

OBFB

ACKB

INTRA

I/O

I/O

ACKA

OBFA

I/O

I/O

I/O

INTRA

STBA

IBFA

ACKA

OBFA

Mode 0

or Mode 1

Only

INPUT CONFIGURATION

D7 D6 D5 D4 D3 D2 D1 D

I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB

OUTPUT CONFIGURATION

D7 D6 D5 D4 D3 D2 D1 D

OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB

FIGURE 15. MODE 1 STATUS WORD FORMAT

D7 D6 D5 D4 D3 D2 D1 D

OBFA INTE1 IBFA INTE2 INTRA X X X

(Defined by Mode 0 or Mode 1 Selection)

FIGURE 16. MODE 2 STATUS WORD FORMAT

GROUP A GROUP B

GROUP A GROUP B

GROUP A GROUP B

FIGURE 19. KEYBOARD AND DISPLAY INTERFACE FIGURE 20. KEYBOARD AND TERMINAL ADDRESS

INTERFACE

FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL FIGURE 22. BASIC CRT CONTROLLER INTERFACE

PA

PA

PA

PA

PA

PA

PA

PA

PC

PC

PB

PB

PB

PB

PB

PB

PB

PB

PC

PC

STROBE

ACK

DATA READY

ACK

MODE 1

(OUTPUT)

82C55A

MODE 1

(INPUT)

FULLY

DECODED

INTERRUPT

REQUEST

INTERRUPT

REQUEST

PC

PC

PC

KEYBOARD

R

R

R

R

R

R

SHIFT

CONTROL

B

B

B

B

B

B

BACKSPACE

CLEAR

BURROUGHS

SELF-SCAN

DISPLAY

BLANKING

CANCEL WORD

STROBE

ACK

FULLY

DECODED

KEYBOARD

R

R

R

R

R

R

SHIFT

CONTROL

PA

PA

PA

PA

PA

PA

PA

PA

PC

PC

PC

PC

PB

PB

PB

PB

PB

PB

PB

PB

MODE 0

(INPUT)

82C55A

MODE 1

(INPUT)

PC

BUST LT

TEST LT

TERMINAL

ADDRESS

INTERRUPT

REQUEST

PA

PA

PA

PA

PA

PA

PA

PA

PC

PC

PC

PC

PC

PC

PC

PB

PB

PB

PC

PC

LSB

STB DATA

MAB

MODE 0

(INPUT)

82C55A

MODE 0

(OUTPUT)

12-BIT

A/D

CONVERTER

(DAC)

PC

PB

PC

PC

BIT

SET/RESET SAMPLE EN

STB

LSB

8-BIT

D/A

CONVERTER

(ADC)

ANALOG

INPUT

ANALOG

OUTPUT

PA

PA

PA

PA

PA

PA

PA

PA

PC

PC

PC

PC

PB

PB

PB

PB

PB

PB

PB

PB

PC

PC

MODE 0

(OUTPUT)

82C55A

MODE 1

(OUTPUT)

PC

DATA READY

ACK

CRT CONTROLLER

• CHARACTER GEN.

INTERRUPT

REQUEST

• REFRESH BUFFER

R

R

R

R

R

R

SHIFT

CONTROL

ROW STB

COLUMN STB

CURSOR H/V STB

CURSOR/ROW/COLUMN

• CURSOR CONTROL

PC

ADDRESS

H&V

BLANKED

BLACK/WHITE

FIGURE 23. BASIC FLOPPY DISC INTERFACE FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE

PA

PA

PA

PA

PA

PA

PA

PA

PC

PC

PC

PC

PB

PB

PB

PB

PB

PB

PB

PB

PC

PC

MODE 0

(OUTPUT)

82C55A

MODE 2

PC

DATA STB

ACK (IN)

FLOPPY DISK

INTERRUPT

REQUEST

D

D

D

D

D

D

D

D

TRACK “0” SENSOR

SYNC READY

INDEX

DATA READY

ACK (OUT)

PC

ENGAGE HEAD

FORWARD/REV.

READ ENABLE

WRITE ENABLE

DISC SELECT

ENABLE CRC

TEST

BUSY LT

CONTROLLER

AND DRIVE

PA

PA

PA

PA

PA

PA

PA

PA

PC

PC

PC

PB

PB

PB

PB

PB

PB

PB

PB

PC

PC

MODE 0

(OUTPUT)

82C55A

MODE 1

PC

STB

ACK

B LEVEL

INTERRUPT

REQUEST

R

R

R

R

R

R

R

R

START/STOP

LIMIT SENSOR (H/V)

OUT OF FLUID

STOP/GO

PC

CHANGE TOOL

LEFT/RIGHT

UP/DOWN

HOR. STEP STROBE

VERT. STEP STROBE

SLEW/STEP

FLUID ENABLE

EMERGENCY STOP

PAPER

TAPE

READER

(INPUT)

MACHINE TOOL

MODE 0

(INPUT)

AC Electrical Specifications V (^) CC = +5V± 10%, GND = 0V; TA = -55 oC to +125oC (M82C55A) (M82C55A-5);

TA = -40 oC to +85o^ C (I82C55A) (I82C55A-5);

TA = 0o^ C to +70o^ C (C82C55A) (C82C55A-5)

SYMBOL PARAMETER

82C55A-5 82C55A

UNITS

TEST

MIN MAX MIN MAX CONDITIONS

READ TIMING

(1) tAR Address Stable Before RD 0 - 0 - ns

(2) tRA Address Stable After RD 0 - 0 - ns

(3) tRR RD Pulse Width 250 - 150 - ns

(4) tRD Data Valid From RD - 200 - 120 ns 1

(5) tDF Data Float After RD 10 75 10 75 ns 2

(6) tRV Time Between RDs and/or WRs 300 - 300 - ns

WRITE TIMING

(7) tAW Address Stable Before WR 0 - 0 - ns

(8) tWA Address Stable After WR 20 - 20 - ns

(9) tWW WR Pulse Width 100 - 100 - ns

(10) tDW Data Valid to WR High 100 - 100 - ns

(11) tWD Data Valid After WR High 30 - 30 - ns

OTHER TIMING

(12) tWB WR = 1 to Output - 350 - 350 ns 1

(13) tIR Peripheral Data Before RD 0 - 0 - ns

(14) tHR Peripheral Data After RD 0 - 0 - ns

(15) tAK ACK Pulse Width 200 - 200 - ns

(16) tST STB Pulse Width 100 - 100 - ns

(17) tPS Peripheral Data Before STB High 20 - 20 - ns

(18) tPH Peripheral Data After STB High 50 - 50 - ns

(19) tAD ACK = 0 to Output - 175 - 175 ns 1

(20) tKD ACK = 1 to Output Float 20 250 20 250 ns 2

(21) tWOB WR = 1 to OBF = 0 - 150 - 150 ns 1

(22) tAOB ACK = 0 to OBF = 1 - 150 - 150 ns 1

(23) tSIB STB = 0 to IBF = 1 - 150 - 150 ns 1

(24) tRIB RD = 1 to IBF = 0 - 150 - 150 ns 1

(25) tRIT RD = 0 to INTR = 0 - 200 - 200 ns 1

(26) tSIT STB = 1 to INTR = 1 - 150 - 150 ns 1

(27) tAIT ACK = 1 to INTR = 1 - 150 - 150 ns 1

(28) tWIT WR = 0 to INTR = 0 - 200 - 200 ns 1

(29) tRES Reset Pulse Width 500 - 500 - ns 1, (Note)

NOTE: Period of initial Reset pulse after power-on must be at least 50μsec. Subsequent Reset pulses may be 500ns minimum.

Timing Waveforms

FIGURE 25. MODE 0 (BASIC INPUT)

FIGURE 26. MODE 0 (BASIC OUTPUT)

FIGURE 27. MODE 1 (STROBED INPUT)

tRA (2)

tHR (14)

tRR (3)

tIR (13)

tAR (1)

tRD (4) tDF (5)

RD

INPUT

CS, A1, A

D7-D

tAW (7) (^) tWA (8)

tWS (12)

tWW (9)

tDW tWD (11)

WR

D7-D

CS, A1, A

OUTPUT

tST (16) STB

INTR

RD

INPUT FROM

IBF

PERIPHERAL

tSIB tSIT

tPH

tPS (17)

tRIT

tRIB (24)