Download Purdue CNIT 176 Final Exam 303: Complete Solutions and Explanations and more Exams Network Programming in PDF only on Docsity!
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Purdue CNIT 176 Final Exam 303
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The Memory Hierarchy from More Costly to Less Costly (CPU) - ANSWER System, Online (Secondary), Tertiary, Off-Line
The Memory Hierarchy from Smaller to Larger (CPU) - ANSWER Registers, Level 1 Cache, Level 2 Cache, Main Memory, Solid-State Disk, Fixed Rigid Disk, Optical Disks (Jukeboxes), Magnetic Tapes (Robotic libraries), USB Flash Drives, Removable Hard Drives
Current CPU Architecture Designs (CPU) - ANSWER • Traditional modern architectures
- Complex Instruction Set Computers (CISC)
- Reduced Instruction Set Computers (RISC)
Current CPU Architecture (CPU) - ANSWER • IBM Mainframe series
- Intel x86 family
- IBM POWER/PowerPC family
- ARM architecture
- Oracle SPARC family
- AMD
CISC (CPU) - ANSWER - Equals a complex instruction set computers.
- Larger vocabulary and uses less steps to complete a task compared to RISC.
RISC (CPU) - ANSWER - Equals a reduced instruction set computers
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- Smaller vocabulary and uses fewer unique instructions to carry out tasks compared to CISC.
Stored Program Computer (CPU) - ANSWER • Modern day computers that store their programs in
electronic memory
- In contrast with historic computers that used wires or
other means of entering program data
- Two architectures support the stored program concept:
The Von Neumann and the Harvard Architectures
- A Plugboard is not a stored program computer.
Von Neumann Architecture (CPU) - ANSWER • It is named after the mathematician and early computer scientist John Von Neumann.
- The computer has single storage system(memory) for storing data as well as program to be executed.
- A single set of address/data buses between CPU and memory.
Von Neumann Bottleneck (CPU) - ANSWER • Processor can process an instruction faster than
it can be transferred in from memory
- So there is time while processor is waiting for
transfer and is sitting idle
- This is the Von Neumann Bottleneck
Harvard Architecture (CPU) - ANSWER • The name is originated from "Harvard Mark I" a relay
based computer, which stored instruction on
punched tape(24 bits wide) and data in electo-mechanical
counters.
- The computer has two separate memories for storing data
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- Scalar Processing
- Superscalar Processing
- Branch Instruction Processing
Fetch Unit (CPU) - ANSWER • Instruction fetch unit
- Instruction decode unit
- Determine opcode
- Identify type of instruction and operands
- Several instructions are fetched in parallel and held in
a buffer until decoded and executed
- Instruction Pointer (IP) register holds instruction
location of current instruction being processed
Execution Unit (CPU) - ANSWER • Receives instructions from the decoder unit
- Appropriate execution unit services the instruction
Sequential Processing (CPU) - ANSWER • One result per m cycles
Pipelining Processing (CPU) - ANSWER • One result per m cycles
- Non-scalar, Scalar, or Superscalar
Instruction Pipelining (CPU) - ANSWER • Assembly line technique to allow overlapping
between fetch-execute cycles of sequences of
instructions
Multiple, Parallel Execution Units (CPU) - ANSWER • Different instructions have different numbers of
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steps in their cycle
- Differences in each step
- Each execution unit is optimized for one general
type of instruction
- Multiple execution units permit simultaneous
execution of several instructions
Scalar Processing (CPU) - ANSWER • Processes only one data item at a time
- Instructions are fetched and decoded in
sequence
- Multiple operations are executed in parallel
- Utilizes pipelining
Superscalar Processing (CPU) - ANSWER • Uses different execution resources (like ALU, or shift register)
- Not separate cores or processors
- Process more than one instruction per clock cycle
- Separate fetch and execute cycles as much as
possible
- Buffers for fetch and decode phases
- Parallel execution units
- Utilizes pipelining
Pipelined (CPU) - ANSWER - Operations are broken down into sub-tasks
- Different sub-tasks from different operations run in
parallel
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Multiprocessing (CPU) - ANSWER Reasons
- Increase the processing power of a system
- Parallel processing through threads: independent
segments of a program that can be executed
concurrently
Multiprocessor system
- Tightly coupled
- Multicore processors—when CPUs are on a single
integrated circuit
- Multiprocessors - requires separate CPU sockets on
same motherboard
Multiprocessor Systems (CPU) - ANSWER Identical access to programs, data, shared
memory, I/O, etc.
Easily extends multi-tasking and redundant
program execution
Two ways to configure
- Hive-drone multiprocessing
- Symmetrical multiprocessing (SMP)
Hive-drone Multiprocessing (CPU) - ANSWER Hive CPU
- Manages the system
- Controls all resources and scheduling
- Assigns tasks to drone CPUs
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Advantages
- Simplicity
- Protection of system and data
Disadvantages
- Master CPU becomes a bottleneck
- Reliability issues—if hive CPU fails, entire
system fails
Symmetrical Multiprocessing (CPU) - ANSWER Each CPU has equal access to resources
Each CPU determines what to run using a standard
algorithm
Disadvantages
- Resource conflicts: memory, I/O, etc.
- Complex implementation
Advantages
- High reliability
- Fault tolerant support is straightforward
- Balanced workload
Cache Memory (CPU) - ANSWER Blocks: between 8 and 64 bytes
Cache Line
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Cache Performance Advantages (CPU) - ANSWER Hit ratios of 90% and above are common
50%+ improved execution speed
Locality of reference is why caching works
- Most memory references confined to small region of
memory at any given time
- Well-written program in small loop, procedure, or
function
- Data likely in array
- Variables stored together
Principle of Locality (CPU) - ANSWER An entire blocks of data is copied after a hit because
the principle of locality tells us that once a byte is
accessed, it is likely that a nearby data element will be
needed soon.
There are three forms of locality:
- Temporal locality- Recently-accessed data elements
tend to be accessed again.
- Spatial locality - Accesses tend to cluster.
- Sequential locality - Instructions tend to be accessed
sequentially.
Temporal Locality (CPU) - ANSWER Recently-accessed data elements
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tend to be accessed again.
Spatial Locality (CPU) - ANSWER Accesses tend to cluster.
Sequential Locality (CPU) - ANSWER Instructions tend to be accessed
sequentially.
Flynn's Taxonomy (CPU) - ANSWER Many attempts have been made to come up with a way
to categorize computer architectures.
Flynn's Taxonomy has been the most enduring of
these, despite having some limitations.
Flynn's Taxonomy takes into consideration the number
of processors and the number of data paths
incorporated into an architecture.
A machine can have one or many processors that
operate on one or many data streams.
The four combinations of multiple processors and
multiple data paths are described by Flynn as:
- SISD: Single instruction stream, single data stream.
These are classic uniprocessor systems.
- SIMD: Single instruction stream, multiple data
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streams. Execute the same instruction on multiple
data values, as in vector processors.
MIMD (CPU) - ANSWER Multiple instruction streams, multiple data
streams. These are today's parallel architectures.
Examples of MIMD architectures are found in
distributed computing, where processing takes place
collaboratively among networked computers.
- A network of workstations (NOW) uses otherwise idle systems to solve a problem.
- A collection of workstations (COW) is a NOW where one
workstation coordinates the actions of the others.
- A dedicated cluster parallel computer (DCPC) is a group of
workstations brought together to solve a specific problem.
- A pile of PCs (POPC) is a cluster of (usually) heterogeneous
systems that form a dedicated parallel system
MISD (CPU) - ANSWER Multiple instruction streams, single data stream.
NOW (CPU) - ANSWER Network of Workstations (NOW) uses otherwise idle systems
to solve a problem.
COW (CPU) - ANSWER Collection of Workstations (COW) is a NOW where one
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workstation coordinates the actions of the others.
DCPC (CPU) - ANSWER Dedicated Cluster Parallel Computer (DCPC) is a group of
workstations brought together to solve a specific problem.
POPC (CPU) - ANSWER Pile of PCs (POPC) is a cluster of (usually) heterogeneous
systems that form a dedicated parallel system.
I/O Processing Speed or Program Execution (I/O) - ANSWER • Determined primarily by ability of I/O operations to
stay ahead of processor
Basic I/O Model (I/O) - ANSWER Input ---> Process ---> Output
I/O Requirements (I/O) - ANSWER • Means for addressing different peripheral devices
- A way for peripheral devices to initiate communication with
the CPU
- An efficient means of transferring data directly between I/O
and memory for large data transfers since programmed I/O
is suitable only for slow devices and individual word
transfers
- Buses that interconnect high-speed I/O devices with the
computer must support high data transfer rates
- Capability of handling devices operating at varying speeds
with varying delays
- Means for handling devices with extremely different control
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- From there it is copied to the appropriate accumulator or general-purpose register, completing the operation.
Interrupt Driven I/O (I/O Technique) (I/O) - ANSWER External input controls
Direct Memory Access Controllers (I/O Technique) (I/O) - ANSWER Method for transferring data between main memory
and a device that bypasses the CPU
Interrupts (I/O) - ANSWER Signal that causes the CPU to alter its normal flow
of instruction execution
- Frees CPU from waiting for events
- Provides control for external I/O initiation
Examples
- unexpected input
- abnormal situation
- illegal instructions
- multitasking, multiprocessing
Interrupt lines (hardware) (I/O) - ANSWER One or more special control lines to the CPU
Interrupt handlers (I/O) - ANSWER • Program that services the interrupt
- Also known as an interrupt routine or device driver
Context (I/O) - ANSWER • Saved registers of a program before control is
transferred to the interrupt handler
- Allows program to resume exactly where it left off
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when control returns to interrupted program
Use of Interrupts (I/O) - ANSWER Notify that an external event has occurred
- Real-time or time-sensitive
Signal completion
- Printer ready or buffer full
Allocate CPU time
Indicate abnormal event (CPU originates for notification
and recovery)
- Illegal operation, hardware error
Software interrupts
Servicing the Interrupt (I/O) - ANSWER 1. Lower priority interrupts are held until higher priority
interrupts are complete
- Suspend program in progress
- Save context, including last instruction executed and
data values in registers, in the PCB or the stack area in
memory
- Branch to interrupt handler program
- Before interrupt arrives, program A is executing. The program counter points to the current instruction.
- When the interrupt is received by the CPU, the current instruction is completed, all the registers are saved in the stack area for in a special area known as a process control block. The PC is loaded with the starting location of a program B, the interrupt handler program. This causes a jump to program B, which becomes the executing program.
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- Conflicts between the CPU and the I/O controller must
be avoided
- Interrupt required for completion
DMA Instructions (I/O) - ANSWER Application program requests I/O service from
operating system
- Privileged programmed I/O instructions
To initiate DMA, programmed I/O is used to send
the following information:
- Location of data on I/O device
- Starting location in memory
- Size of the block
- Direction of transfer: read or write
Interrupt to CPU upon completion of DMA
DMA Initiation and Control (I/O) - ANSWER 1. Programmed I/O used to prepare disk controller for transfer by providing required information and initiating transfer.
- DMA transfer. In this case data is transferred from disk to memory.
- Upon completion, disk controller sends completion interrupt to CPU.
I/O Controller Functions (I/O) - ANSWER • Recognizes messages from device(s) addressed to it and
accepts commands from the CPU
- Provides a buffer where the data from memory can be
held until it can be transferred to the device
- Provides the necessary registers and controls to perform
a direct memory transfer
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- Physically controls the device
- Copies data from its buffer to the device/from the CPU to
its buffer
Peripherals (Peripherals) - ANSWER Devices that are separate from the basic computer
- Not the CPU, memory, or power source
Classified as input, output, and storage
Connect via
- Ports
- Interface to system bus
Storage Devices (Peripherals) - ANSWER Secondary storage
- Online storage
- Offline storage - loaded when needed
- Network file storage
- File servers, web servers, database servers
Plash Memory (Peripherals) - ANSWER • Solid-state drives
- Large capacity flash memory units
- Generally replacing magnetic disk drives as long-term
storage
- Relatively immune to physical shocks
- Generates little heat or noise
