Single-Cycle Processor - Computer Organization and Design - Lecture Slides, Slides of Computer Aided Design (CAD)

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Single-Cycle Processor

Apps

O/S

Arch

mArch

Logic

Digital

Analog

Devices

Physics

Logic Design Toolbox

• Basic Logic gates

• AND, OR, NOT, etc.

• Registers

– and register files

• Arithmetic-Logic Unit (ALU)

– Also, adders of various types

• Memory

– Generic model

Single-Cycle LC2k7 Datapath

Instruction MEM

Data MEM

Register File

A

L

U

Register File

Sign Ext.

A

D

A D

D

D

P

C

Instruction Bits

ZD

Branch

ZD

Sign Extension

• To “extend” a 16-bit offset to its 32-bit

version, we can replicate the top bit.

– This preserves the sign of the number

Sign Ext.

Test Yourself

• Some have suggested that the lw instruction would be

more easily used if it permitted the R-type format:

lw dstReg regA regB

• What changes (if any) would need to be made to the data

path of the single cycle CPU to implement this change?

Test Yourself

• Some have suggested that the sw instruction would be

more easily used if it permitted the R-type format:

sw rs regA regB

• What changes (if any) would need to be made to the data

path of the single cycle CPU to implement this change?

Control Signals (from left to right)

• PCSrc (2 bits)

– Combination of Branch, Jump, and ZD signals

• ALU2Reg (2 bits)

• RegDst

• RegWrite

• ALUSrc

• MemWrite

• ALU Operation

(the following tables assume MUXes are numbered from top to

bottom)

Controls For add

PCSrc ALU2Reg RegDst RegWrite ALUSrc MemWrite ALU Op

add 00 01 0 1 0 0 “add”

Test Yourself

• Modify the single cycle machine design by implementing

the instruction addi

• Show each new data path and control signal, and list the values

for each control signal that would be required to make this work

addi rA rB immed.

rA = rB + immed.